)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f",
  "path": "manual/CHAPTER_Verilog.tex"
}