)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "a9efd2e81cd502665ee034f64c85b11e34dfd9bb",
  "path": "manual/CHAPTER_Verilog.tex"
}