)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "ab0fb19cfff7760bfd69b49ed6d81a823be2a6ba",
  "path": "manual/CHAPTER_Verilog.tex"
}