)]}'
{
  "id": "f89a7980402c32a09f21a5b4aa2f9b315f354ac2",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "aadbcdcdd51512e5917e74772f92ba667c81ac0f",
      "name": ".gitignore"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6a8462b4189ab968a98235f2095e5da6e72464ec",
      "name": "Makefile.inc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "49281f7e79e6874bf16f3b523b28adb90c0c240c",
      "name": "const2ast.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7e107dc267b8cff6b7fbaa5c2cfac02586824243",
      "name": "preproc.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "058d750c394522a2911edcb43be4f75cb8872e21",
      "name": "verilog_frontend.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "a7c9b2fe6ab71303f037d7c0ee5dfb2896766d76",
      "name": "verilog_frontend.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f4a0484d7a66c8e36d9c324e986100f43a5f2205",
      "name": "verilog_lexer.l"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "1758354c5ee42cdc6021b781e6e5d97262011200",
      "name": "verilog_parser.y"
    }
  ]
}
