read_verilog <<EOT
module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
module latch (input e, d, output q); endmodule
module clkgen (output o); endmodule

module top(input clk1, clk2, clk3, d, e, output [4:0] q);
wire clk4, clk5, clk6;
dff s0 (.clk(clk1), .d(d), .q(q[0]));
dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
latch s2 (.e(clk3), .d(d), .q(q[2]));
sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3]));
dff s4 (.clk(clk4), .d(d), .q(q[4]));
dff s5 (.clk(clk5), .d(d), .q(q[4]));
dff s6 (.clk(clk6), .d(d), .q(q[4]));
endmodule

module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
wire tmp;
clkgen s7(.o(sclk4));
clkgen s8(.o(sclk5));
clkgen s9(.o(tmp));
clkbuf s10(.i(tmp), .o(sclk6));
dff s11(.clk(sclk4), .d(sd), .q(sq));
endmodule
EOT

hierarchy -auto-top
design -save ref

# ----------------------

design -load ref
clkbufmap -buf clkbuf o:i
select -assert-count 3 top/t:clkbuf
select -assert-count 2 sub/t:clkbuf
select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
select -assert-count 1 @clk1                        # Check there is one such fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
select -set clk2 w:clk2 %a %co t:clkbuf %i
select -assert-count 1 @clk2
select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
select -set clk5 w:clk5 %a %ci t:clkbuf %i
select -assert-count 1 @clk5
select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
select -assert-count 1 @sclk4
select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i

# ----------------------

design -load ref
setattr -set clkbuf_inhibit 0 w:clk1
setattr -set clkbuf_inhibit 1 w:clk2
clkbufmap -buf clkbuf o:i
select -assert-count 2 top/t:clkbuf
select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
select -assert-count 1 @clk1                        # Check there is one such fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
select -assert-count 0 w:clk2 %a %co t:clkbuf %i

# ----------------------

design -load ref
setattr -set clkbuf_inhibit 1 w:clk1
setattr -set buffer_type "bufg" w:clk2
clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
select -assert-count 3 top/t:clkbuf
select -assert-count 2 sub/t:clkbuf
select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
select -assert-count 1 @clk1                        # Check there is one such fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
select -set clk2 w:clk2 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
select -assert-count 1 @clk2                        # Check there is one such fanout
select -assert-count 1 @clk2 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i    # And that one fanout is 's0'

# ----------------------

design -load ref
setattr -set buffer_type "none" w:clk1
setattr -set buffer_type "bufr" w:clk2
setattr -set buffer_type "bufr" w:sclk4
setattr -set buffer_type "bufr" w:sclk5
clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
select -assert-count 0 w:clk1 %a %co t:clkbuf %i
select -assert-count 0 w:clk2 %a %co t:clkbuf %i
select -assert-count 0 top/t:clkbuf
select -assert-count 1 sub/t:clkbuf