)]}'
{
  "commit": "c4bd318e76240d3e6a95109c19641cdfd86517b8",
  "tree": "652f7209fd5b65045084914b04f98fbbaecede3e",
  "parents": [
    "5110a34dd74bc96c47d4aef47bc155110de2d87e"
  ],
  "author": {
    "name": "Marcin Kościelnicki",
    "email": "koriakin@0x04.net",
    "time": "Fri Nov 01 14:00:15 2019 +0000"
  },
  "committer": {
    "name": "Marcin Kościelnicki",
    "email": "mwk@0x04.net",
    "time": "Wed Nov 06 15:11:27 2019 +0100"
  },
  "message": "synth_xilinx: Merge blackbox primitive libraries.\n\nFirst, there are no longer separate cell libraries for xc6s/xc7/xcu.\nManually instantiating a primitive for a \"wrong\" family will result\nin yosys passing it straight through to the output, and it will be\neither upgraded or rejected by the P\u0026R tool.\n\nSecond, the blackbox library is expanded to cover many more families:\neverything from Spartan 3 up is included.  Primitives for Virtex and\nVirtex 2 are listed in the Python file as well if we ever want to\ninclude them, but that would require having two different ISE versions\n(10.1 and 14.7) available when running cells_xtra.py, and so is probably\nmore trouble than it\u0027s worth.\n\nThird, the blockram blackboxes are no longer in separate files — there\nis no practical reason to do so (from synthesis PoV, they are no\ndifferent from any other cells_xtra blackbox), and they needlessly\ncomplicated the flow (among other things, merging them allows the user\nto use eg. Series 7 primitives and have them auto-upgraded to\nUltrascale).\n\nLast, since xc5v logic synthesis appears to work reasonably well\n(the only major problem is lack of blockram inference support), xc5v is\nnow an accepted setting for the -family option.\n",
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