diff --git a/Makefile b/Makefile
index 70d683c..a24f19b 100644
--- a/Makefile
+++ b/Makefile
@@ -713,12 +713,12 @@
 	+cd tests/opt && bash run-test.sh
 	+cd tests/aiger && bash run-test.sh $(ABCOPT)
 	+cd tests/arch && bash run-test.sh
-	+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/ice40 && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/xilinx && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/efinix && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
-	+cd tests/efinix && bash run-test.sh $(SEEDOPT)
-	+cd tests/anlogic && bash run-test.sh $(SEEDOPT)
-	+cd tests/ecp5 && bash run-test.sh $(SEEDOPT)
-	+cd tests/xilinx && bash run-test.sh $(SEEDOPT)
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/anlogic/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/anlogic/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/anlogic/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/anlogic/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule
diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/anlogic/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v
deleted file mode 100644
index 27bc0bf..0000000
--- a/tests/anlogic/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v
deleted file mode 100644
index 90dd314..0000000
--- a/tests/anlogic/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
diff --git a/tests/anlogic/.gitignore b/tests/arch/anlogic/.gitignore
similarity index 100%
rename from tests/anlogic/.gitignore
rename to tests/arch/anlogic/.gitignore
diff --git a/tests/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys
similarity index 92%
rename from tests/anlogic/add_sub.ys
rename to tests/arch/anlogic/add_sub.ys
index b8b67cc..5396ce7 100644
--- a/tests/anlogic/add_sub.ys
+++ b/tests/arch/anlogic/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
diff --git a/tests/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
similarity index 92%
rename from tests/anlogic/counter.ys
rename to tests/arch/anlogic/counter.ys
index 036fdba..d363ec2 100644
--- a/tests/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys
similarity index 95%
rename from tests/anlogic/dffs.ys
rename to tests/arch/anlogic/dffs.ys
index 9cbe5fc..d3281ab 100644
--- a/tests/anlogic/dffs.ys
+++ b/tests/arch/anlogic/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
similarity index 95%
rename from tests/anlogic/fsm.ys
rename to tests/arch/anlogic/fsm.ys
index 452ef92..f45951b 100644
--- a/tests/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 #flatten
diff --git a/tests/anlogic/latches.ys b/tests/arch/anlogic/latches.ys
similarity index 96%
rename from tests/anlogic/latches.ys
rename to tests/arch/anlogic/latches.ys
index c00c7a2..8d66f77 100644
--- a/tests/anlogic/latches.ys
+++ b/tests/arch/anlogic/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys
new file mode 100644
index 0000000..125ee5d
--- /dev/null
+++ b/tests/arch/anlogic/logic.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
diff --git a/tests/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
similarity index 95%
rename from tests/anlogic/memory.ys
rename to tests/arch/anlogic/memory.ys
index 8c0ce84..87b93c2 100644
--- a/tests/anlogic/memory.ys
+++ b/tests/arch/anlogic/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
diff --git a/tests/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
similarity index 97%
rename from tests/anlogic/mux.ys
rename to tests/arch/anlogic/mux.ys
index 64ed2a2..3d5fe7c 100644
--- a/tests/anlogic/mux.ys
+++ b/tests/arch/anlogic/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh
similarity index 74%
rename from tests/anlogic/run-test.sh
rename to tests/arch/anlogic/run-test.sh
index 46716f9..bf19b88 100755
--- a/tests/anlogic/run-test.sh
+++ b/tests/arch/anlogic/run-test.sh
@@ -6,7 +6,7 @@
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys
similarity index 91%
rename from tests/anlogic/shifter.ys
rename to tests/arch/anlogic/shifter.ys
index 5eaed30..12df44b 100644
--- a/tests/anlogic/shifter.ys
+++ b/tests/arch/anlogic/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys
similarity index 91%
rename from tests/anlogic/tribuf.ys
rename to tests/arch/anlogic/tribuf.ys
index 0eb1338..eaa0737 100644
--- a/tests/anlogic/tribuf.ys
+++ b/tests/arch/anlogic/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten
diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v
new file mode 100644
index 0000000..77e5f57
--- /dev/null
+++ b/tests/arch/common/add_sub.v
@@ -0,0 +1,12 @@
+module top
+(
+    input [3:0] x,
+    input [3:0] y,
+
+    output [3:0] A,
+    output [3:0] B
+);
+
+    assign A =  x + y;
+    assign B =  x - y;
+endmodule
diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
new file mode 100644
index 0000000..576bd81
--- /dev/null
+++ b/tests/arch/common/adffs.v
@@ -0,0 +1,43 @@
+module adff( input d, clk, clr, output reg q );
+    initial begin
+        q = 0;
+    end
+	  always @( posedge clk, posedge clr )
+      if ( clr )
+        q <= 1'b0;
+      else
+        q <= d;
+endmodule
+
+module adffn( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	  always @( posedge clk, negedge clr )
+		  if ( !clr )
+			  q <= 1'b0;
+  		else
+        q <= d;
+endmodule
+
+module dffs( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+    always @( posedge clk )
+      if ( pre )
+        q <= 1'b1;
+      else
+        q <= d;
+endmodule
+
+module ndffnr( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+    always @( negedge clk )
+      if ( !clr )
+        q <= 1'b0;
+      else
+        q <= d;
+endmodule
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
new file mode 100644
index 0000000..9746fd7
--- /dev/null
+++ b/tests/arch/common/counter.v
@@ -0,0 +1,11 @@
+module top ( out, clk, reset );
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+      if (reset)
+          out <= 8'b0;
+      else
+          out <= out + 1;
+endmodule
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
new file mode 100644
index 0000000..636252d
--- /dev/null
+++ b/tests/arch/common/dffs.v
@@ -0,0 +1,13 @@
+module dff ( input d, clk, output reg q );
+	  always @( posedge clk )
+        q <= d;
+endmodule
+
+module dffe( input d, clk, en, output reg q );
+    initial begin
+        q = 0;
+    end
+	  always @( posedge clk )
+        if ( en )
+              q <= d;
+endmodule
diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
new file mode 100644
index 0000000..9d3fbb6
--- /dev/null
+++ b/tests/arch/common/fsm.v
@@ -0,0 +1,51 @@
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+    input   clock,reset,req_0,req_1;
+    output  gnt_0,gnt_1;
+    wire    clock,reset,req_0,req_1;
+    reg     gnt_0,gnt_1;
+
+    parameter SIZE = 3;
+    parameter IDLE = 3'b001;
+    parameter GNT0 = 3'b010;
+    parameter GNT1 = 3'b100;
+    parameter GNT2 = 3'b101;
+
+    reg [SIZE-1:0] state;
+    reg [SIZE-1:0] next_state;
+
+    always @ (posedge clock)
+        begin : FSM
+          if (reset == 1'b1) begin
+            state <=  #1  IDLE;
+            gnt_0 <= 0;
+            gnt_1 <= 0;
+          end 
+          else
+            case(state)
+              IDLE :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                          gnt_0 <= 1;
+                      end else if (req_1 == 1'b1) begin
+                          gnt_1 <= 1;
+                          state <=  #1  GNT0;
+                      end else begin
+                          state <=  #1  IDLE;
+                      end
+              GNT0 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                      end else begin
+                          gnt_0 <= 0;
+                          state <=  #1  IDLE;
+                      end
+              GNT1 :  if (req_1 == 1'b1) begin
+                          state <=  #1  GNT2;
+                          gnt_1 <= req_0;
+                      end
+              GNT2 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT1;
+                          gnt_1 <= req_1;
+                      end
+              default : state <=  #1  IDLE;
+            endcase
+        end
+endmodule
diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v
new file mode 100644
index 0000000..60b7571
--- /dev/null
+++ b/tests/arch/common/latches.v
@@ -0,0 +1,21 @@
+module latchp ( input d, clk, en, output reg q );
+	always @*
+		if ( en )
+			q <= d;
+endmodule
+
+module latchn ( input d, clk, en, output reg q );
+	always @*
+		if ( !en )
+			q <= d;
+endmodule
+
+module latchsr ( input d, clk, en, clr, pre, output reg q );
+	always @*
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+			q <= d;
+endmodule
diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v
new file mode 100644
index 0000000..c17899f
--- /dev/null
+++ b/tests/arch/common/logic.v
@@ -0,0 +1,16 @@
+module top
+(
+    input [0:7] in,
+    output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+);
+    assign B1 =  in[0] & in[1];
+    assign B2 =  in[0] | in[1];
+    assign B3 =  in[0] ~& in[1];
+    assign B4 =  in[0] ~| in[1];
+    assign B5 =  in[0] ^ in[1];
+    assign B6 =  in[0] ~^ in[1];
+    assign B7 =  ~in[0];
+    assign B8 =  in[0];
+    assign B9 =  in[0:1] && in [2:3];
+    assign B10 =  in[0:1] || in [2:3];
+endmodule
diff --git a/tests/anlogic/memory.v b/tests/arch/common/memory.v
similarity index 100%
rename from tests/anlogic/memory.v
rename to tests/arch/common/memory.v
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v
new file mode 100644
index 0000000..437a91c
--- /dev/null
+++ b/tests/arch/common/mul.v
@@ -0,0 +1,9 @@
+module top
+(
+    input [5:0] x,
+    input [5:0] y,
+
+    output [11:0] A,
+);
+    assign A =  x * y;
+endmodule
diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v
new file mode 100644
index 0000000..71c1ac7
--- /dev/null
+++ b/tests/arch/common/mux.v
@@ -0,0 +1,60 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+    input[1:0] S;
+    input[3:0] D;
+    output Y;
+
+    reg Y;
+    wire[1:0] S;
+    wire[3:0] D;
+
+    always @*
+    begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+        endcase
+    end
+endmodule
+
+module mux8 ( S, D, Y );
+    input[2:0] S;
+    input[7:0] D;
+    output Y;
+
+    reg Y;
+    wire[2:0] S;
+    wire[7:0] D;
+
+    always @*
+    begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            4 : Y = D[4];
+            5 : Y = D[5];
+            6 : Y = D[6];
+            7 : Y = D[7];
+        endcase
+    end
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+    assign Y = D[S];
+endmodule
diff --git a/tests/anlogic/shifter.v b/tests/arch/common/shifter.v
similarity index 80%
rename from tests/anlogic/shifter.v
rename to tests/arch/common/shifter.v
index 04ae49d..cace3b5 100644
--- a/tests/anlogic/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,8 +1,4 @@
-module top    (
-out,
-clk,
-in
-);
+module top(out, clk, in);
     output [7:0] out;
     input signed clk, in;
     reg signed [7:0] out = 0;
@@ -11,6 +7,5 @@
 	begin
 		out    <= out >> 1;
 		out[7] <= in;
-	end
-
+	end    
 endmodule
diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v
new file mode 100644
index 0000000..e1d7016
--- /dev/null
+++ b/tests/arch/common/tribuf.v
@@ -0,0 +1,8 @@
+module tristate(en, i, o);
+    input en;
+    input i;
+    output reg o;
+
+    always @(en or i)
+        o <= (en)? i : 1'bZ;
+endmodule
diff --git a/tests/ecp5/.gitignore b/tests/arch/ecp5/.gitignore
similarity index 100%
rename from tests/ecp5/.gitignore
rename to tests/arch/ecp5/.gitignore
diff --git a/tests/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys
similarity index 90%
rename from tests/ecp5/add_sub.ys
rename to tests/arch/ecp5/add_sub.ys
index ee72d73..d85ce79 100644
--- a/tests/ecp5/add_sub.ys
+++ b/tests/arch/ecp5/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
diff --git a/tests/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys
similarity index 97%
rename from tests/ecp5/adffs.ys
rename to tests/arch/ecp5/adffs.ys
index c6780e5..01605df 100644
--- a/tests/ecp5/adffs.ys
+++ b/tests/arch/ecp5/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/ecp5/counter.ys b/tests/arch/ecp5/counter.ys
similarity index 91%
rename from tests/ecp5/counter.ys
rename to tests/arch/ecp5/counter.ys
index 8ef7077..f9f60fb 100644
--- a/tests/ecp5/counter.ys
+++ b/tests/arch/ecp5/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys
similarity index 95%
rename from tests/ecp5/dffs.ys
rename to tests/arch/ecp5/dffs.ys
index a4f45d2..be97972 100644
--- a/tests/ecp5/dffs.ys
+++ b/tests/arch/ecp5/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/ecp5/dpram.v b/tests/arch/ecp5/dpram.v
similarity index 100%
rename from tests/ecp5/dpram.v
rename to tests/arch/ecp5/dpram.v
diff --git a/tests/ecp5/dpram.ys b/tests/arch/ecp5/dpram.ys
similarity index 100%
rename from tests/ecp5/dpram.ys
rename to tests/arch/ecp5/dpram.ys
diff --git a/tests/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys
similarity index 93%
rename from tests/ecp5/fsm.ys
rename to tests/arch/ecp5/fsm.ys
index ded91e5..f834a4c 100644
--- a/tests/ecp5/fsm.ys
+++ b/tests/arch/ecp5/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
diff --git a/tests/ecp5/latches.ys b/tests/arch/ecp5/latches.ys
similarity index 95%
rename from tests/ecp5/latches.ys
rename to tests/arch/ecp5/latches.ys
index fc15a69..3d011d7 100644
--- a/tests/ecp5/latches.ys
+++ b/tests/arch/ecp5/latches.ys
@@ -1,5 +1,4 @@
-
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/ecp5/logic.ys b/tests/arch/ecp5/logic.ys
similarity index 91%
rename from tests/ecp5/logic.ys
rename to tests/arch/ecp5/logic.ys
index 4f113a1..3298b19 100644
--- a/tests/ecp5/logic.ys
+++ b/tests/arch/ecp5/logic.ys
@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
diff --git a/tests/ecp5/macc.v b/tests/arch/ecp5/macc.v
similarity index 100%
rename from tests/ecp5/macc.v
rename to tests/arch/ecp5/macc.v
diff --git a/tests/ecp5/macc.ys b/tests/arch/ecp5/macc.ys
similarity index 100%
rename from tests/ecp5/macc.ys
rename to tests/arch/ecp5/macc.ys
diff --git a/tests/ecp5/memory.ys b/tests/arch/ecp5/memory.ys
similarity index 94%
rename from tests/ecp5/memory.ys
rename to tests/arch/ecp5/memory.ys
index 9b475f1..c82b7b4 100644
--- a/tests/ecp5/memory.ys
+++ b/tests/arch/ecp5/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
diff --git a/tests/ecp5/mul.ys b/tests/arch/ecp5/mul.ys
similarity index 93%
rename from tests/ecp5/mul.ys
rename to tests/arch/ecp5/mul.ys
index 0a91f89..2105be5 100644
--- a/tests/ecp5/mul.ys
+++ b/tests/arch/ecp5/mul.ys
@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 # Blocked by issue #1358 (Missing ECP5 simulation models)
diff --git a/tests/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
similarity index 97%
rename from tests/ecp5/mux.ys
rename to tests/arch/ecp5/mux.ys
index 8cfbd54..92463aa 100644
--- a/tests/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/ecp5/rom.v b/tests/arch/ecp5/rom.v
similarity index 100%
rename from tests/ecp5/rom.v
rename to tests/arch/ecp5/rom.v
diff --git a/tests/ecp5/rom.ys b/tests/arch/ecp5/rom.ys
similarity index 100%
rename from tests/ecp5/rom.ys
rename to tests/arch/ecp5/rom.ys
diff --git a/tests/anlogic/run-test.sh b/tests/arch/ecp5/run-test.sh
similarity index 74%
copy from tests/anlogic/run-test.sh
copy to tests/arch/ecp5/run-test.sh
index 46716f9..bf19b88 100755
--- a/tests/anlogic/run-test.sh
+++ b/tests/arch/ecp5/run-test.sh
@@ -6,7 +6,7 @@
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys
similarity index 91%
rename from tests/ecp5/shifter.ys
rename to tests/arch/ecp5/shifter.ys
index e1901e1..3f0079f 100644
--- a/tests/ecp5/shifter.ys
+++ b/tests/arch/ecp5/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys
similarity index 91%
rename from tests/ecp5/tribuf.ys
rename to tests/arch/ecp5/tribuf.ys
index a6e9c95..0118705 100644
--- a/tests/ecp5/tribuf.ys
+++ b/tests/arch/ecp5/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten
diff --git a/tests/efinix/.gitignore b/tests/arch/efinix/.gitignore
similarity index 100%
rename from tests/efinix/.gitignore
rename to tests/arch/efinix/.gitignore
diff --git a/tests/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys
similarity index 91%
rename from tests/efinix/add_sub.ys
rename to tests/arch/efinix/add_sub.ys
index 8bd28c6..20523c0 100644
--- a/tests/efinix/add_sub.ys
+++ b/tests/arch/efinix/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
diff --git a/tests/efinix/adffs.ys b/tests/arch/efinix/adffs.ys
similarity index 97%
rename from tests/efinix/adffs.ys
rename to tests/arch/efinix/adffs.ys
index 1069c6c..49dc7f2 100644
--- a/tests/efinix/adffs.ys
+++ b/tests/arch/efinix/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/efinix/counter.ys b/tests/arch/efinix/counter.ys
similarity index 92%
rename from tests/efinix/counter.ys
rename to tests/arch/efinix/counter.ys
index 82e61d3..d20b8ae 100644
--- a/tests/efinix/counter.ys
+++ b/tests/arch/efinix/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/efinix/dffs.ys b/tests/arch/efinix/dffs.ys
similarity index 96%
rename from tests/efinix/dffs.ys
rename to tests/arch/efinix/dffs.ys
index cdd2882..af787ab 100644
--- a/tests/efinix/dffs.ys
+++ b/tests/arch/efinix/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
similarity index 94%
rename from tests/efinix/fsm.ys
rename to tests/arch/efinix/fsm.ys
index 2ec7521..a8ba70f 100644
--- a/tests/efinix/fsm.ys
+++ b/tests/arch/efinix/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
diff --git a/tests/efinix/latches.ys b/tests/arch/efinix/latches.ys
similarity index 95%
rename from tests/efinix/latches.ys
rename to tests/arch/efinix/latches.ys
index 899d024..1b1c000 100644
--- a/tests/efinix/latches.ys
+++ b/tests/arch/efinix/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/efinix/logic.ys b/tests/arch/efinix/logic.ys
similarity index 91%
rename from tests/efinix/logic.ys
rename to tests/arch/efinix/logic.ys
index fdedb33..76e98e0 100644
--- a/tests/efinix/logic.ys
+++ b/tests/arch/efinix/logic.ys
@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
diff --git a/tests/efinix/memory.ys b/tests/arch/efinix/memory.ys
similarity index 94%
rename from tests/efinix/memory.ys
rename to tests/arch/efinix/memory.ys
index fe24b0a..6f6acdc 100644
--- a/tests/efinix/memory.ys
+++ b/tests/arch/efinix/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
diff --git a/tests/efinix/mux.ys b/tests/arch/efinix/mux.ys
similarity index 97%
rename from tests/efinix/mux.ys
rename to tests/arch/efinix/mux.ys
index 71a9681..b46f641 100644
--- a/tests/efinix/mux.ys
+++ b/tests/arch/efinix/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/anlogic/run-test.sh b/tests/arch/efinix/run-test.sh
similarity index 74%
copy from tests/anlogic/run-test.sh
copy to tests/arch/efinix/run-test.sh
index 46716f9..bf19b88 100755
--- a/tests/anlogic/run-test.sh
+++ b/tests/arch/efinix/run-test.sh
@@ -6,7 +6,7 @@
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/efinix/shifter.ys b/tests/arch/efinix/shifter.ys
similarity index 91%
rename from tests/efinix/shifter.ys
rename to tests/arch/efinix/shifter.ys
index 1a6b556..54f7116 100644
--- a/tests/efinix/shifter.ys
+++ b/tests/arch/efinix/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys
similarity index 92%
rename from tests/efinix/tribuf.ys
rename to tests/arch/efinix/tribuf.ys
index 2e2ab9e..47904f2 100644
--- a/tests/efinix/tribuf.ys
+++ b/tests/arch/efinix/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf
diff --git a/tests/ice40/.gitignore b/tests/arch/ice40/.gitignore
similarity index 100%
rename from tests/ice40/.gitignore
rename to tests/arch/ice40/.gitignore
diff --git a/tests/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys
similarity index 91%
rename from tests/ice40/add_sub.ys
rename to tests/arch/ice40/add_sub.ys
index 4a998d9..578ec08 100644
--- a/tests/ice40/add_sub.ys
+++ b/tests/arch/ice40/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys
new file mode 100644
index 0000000..e5dbabb
--- /dev/null
+++ b/tests/arch/ice40/adffs.ys
@@ -0,0 +1,39 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-none t:SB_DFFR %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFSS
+select -assert-none t:SB_DFFSS %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/counter.ys b/tests/arch/ice40/counter.ys
similarity index 92%
rename from tests/ice40/counter.ys
rename to tests/arch/ice40/counter.ys
index c65c216..f112eb9 100644
--- a/tests/ice40/counter.ys
+++ b/tests/arch/ice40/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys
new file mode 100644
index 0000000..b28a5a9
--- /dev/null
+++ b/tests/arch/ice40/dffs.ys
@@ -0,0 +1,19 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFFE %% t:* %D
\ No newline at end of file
diff --git a/tests/ice40/dpram.v b/tests/arch/ice40/dpram.v
similarity index 100%
rename from tests/ice40/dpram.v
rename to tests/arch/ice40/dpram.v
diff --git a/tests/ice40/dpram.ys b/tests/arch/ice40/dpram.ys
similarity index 100%
rename from tests/ice40/dpram.ys
rename to tests/arch/ice40/dpram.ys
diff --git a/tests/ice40/fsm.ys b/tests/arch/ice40/fsm.ys
similarity index 77%
rename from tests/ice40/fsm.ys
rename to tests/arch/ice40/fsm.ys
index 4cc8629..5aacc6c 100644
--- a/tests/ice40/fsm.ys
+++ b/tests/arch/ice40/fsm.ys
@@ -1,10 +1,10 @@
-read_verilog fsm.v
-hierarchy -top top
+read_verilog ../common/fsm.v
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 2 t:SB_DFFESR
 select -assert-count 2 t:SB_DFFSR
diff --git a/tests/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
similarity index 100%
rename from tests/ice40/ice40_opt.ys
rename to tests/arch/ice40/ice40_opt.ys
diff --git a/tests/efinix/latches.ys b/tests/arch/ice40/latches.ys
similarity index 66%
copy from tests/efinix/latches.ys
copy to tests/arch/ice40/latches.ys
index 899d024..b06dd63 100644
--- a/tests/efinix/latches.ys
+++ b/tests/arch/ice40/latches.ys
@@ -1,33 +1,33 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_ice40
 cd latchp # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_LUT4
+select -assert-count 1 t:SB_LUT4
 
-select -assert-none t:EFX_LUT4 %% t:* %D
+select -assert-none t:SB_LUT4 %% t:* %D
 
 
 design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_ice40
 cd latchn # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_LUT4
+select -assert-count 1 t:SB_LUT4
 
-select -assert-none t:EFX_LUT4 %% t:* %D
+select -assert-none t:SB_LUT4 %% t:* %D
 
 
 design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_ice40
 cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:EFX_LUT4
+select -assert-count 2 t:SB_LUT4
 
-select -assert-none t:EFX_LUT4 %% t:* %D
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/logic.ys b/tests/arch/ice40/logic.ys
similarity index 91%
rename from tests/ice40/logic.ys
rename to tests/arch/ice40/logic.ys
index fc5e5b1..7432f5b 100644
--- a/tests/ice40/logic.ys
+++ b/tests/arch/ice40/logic.ys
@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
diff --git a/tests/ice40/macc.v b/tests/arch/ice40/macc.v
similarity index 100%
rename from tests/ice40/macc.v
rename to tests/arch/ice40/macc.v
diff --git a/tests/ice40/macc.ys b/tests/arch/ice40/macc.ys
similarity index 100%
rename from tests/ice40/macc.ys
rename to tests/arch/ice40/macc.ys
diff --git a/tests/ice40/memory.ys b/tests/arch/ice40/memory.ys
similarity index 91%
rename from tests/ice40/memory.ys
rename to tests/arch/ice40/memory.ys
index a66afba..c356e67 100644
--- a/tests/ice40/memory.ys
+++ b/tests/arch/ice40/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
diff --git a/tests/ice40/mul.ys b/tests/arch/ice40/mul.ys
similarity index 91%
rename from tests/ice40/mul.ys
rename to tests/arch/ice40/mul.ys
index 8a0822a..9891b77 100644
--- a/tests/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys
@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys
new file mode 100644
index 0000000..9982239
--- /dev/null
+++ b/tests/arch/ice40/mux.ys
@@ -0,0 +1,40 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/rom.v b/tests/arch/ice40/rom.v
similarity index 100%
rename from tests/ice40/rom.v
rename to tests/arch/ice40/rom.v
diff --git a/tests/ice40/rom.ys b/tests/arch/ice40/rom.ys
similarity index 100%
rename from tests/ice40/rom.ys
rename to tests/arch/ice40/rom.ys
diff --git a/tests/anlogic/run-test.sh b/tests/arch/ice40/run-test.sh
similarity index 74%
copy from tests/anlogic/run-test.sh
copy to tests/arch/ice40/run-test.sh
index 46716f9..bf19b88 100755
--- a/tests/anlogic/run-test.sh
+++ b/tests/arch/ice40/run-test.sh
@@ -6,7 +6,7 @@
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/ice40/shifter.ys b/tests/arch/ice40/shifter.ys
similarity index 90%
rename from tests/ice40/shifter.ys
rename to tests/arch/ice40/shifter.ys
index 47d95d2..08ea64f 100644
--- a/tests/ice40/shifter.ys
+++ b/tests/arch/ice40/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/anlogic/tribuf.ys b/tests/arch/ice40/tribuf.ys
similarity index 66%
copy from tests/anlogic/tribuf.ys
copy to tests/arch/ice40/tribuf.ys
index 0eb1338..10cded9 100644
--- a/tests/anlogic/tribuf.ys
+++ b/tests/arch/ice40/tribuf.ys
@@ -1,8 +1,10 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
+tribuf
 flatten
-equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
+synth
+equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
diff --git a/tests/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
similarity index 100%
rename from tests/ice40/wrapcarry.ys
rename to tests/arch/ice40/wrapcarry.ys
diff --git a/tests/xilinx/.gitignore b/tests/arch/xilinx/.gitignore
similarity index 100%
rename from tests/xilinx/.gitignore
rename to tests/arch/xilinx/.gitignore
diff --git a/tests/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
similarity index 92%
rename from tests/xilinx/add_sub.ys
rename to tests/arch/xilinx/add_sub.ys
index f06e7fa..9dbddce 100644
--- a/tests/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
similarity index 97%
rename from tests/xilinx/adffs.ys
rename to tests/arch/xilinx/adffs.ys
index 1923b98..12c3441 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
similarity index 93%
rename from tests/xilinx/counter.ys
rename to tests/arch/xilinx/counter.ys
index 4595416..57b645d 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
similarity index 95%
rename from tests/xilinx/dffs.ys
rename to tests/arch/xilinx/dffs.ys
index f1716da..0bba485 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/xilinx/dsp_simd.ys b/tests/arch/xilinx/dsp_simd.ys
similarity index 100%
rename from tests/xilinx/dsp_simd.ys
rename to tests/arch/xilinx/dsp_simd.ys
diff --git a/tests/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
similarity index 94%
rename from tests/xilinx/fsm.ys
rename to tests/arch/xilinx/fsm.ys
index a9e94c2..d2b4814 100644
--- a/tests/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
diff --git a/tests/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
similarity index 96%
rename from tests/xilinx/latches.ys
rename to tests/arch/xilinx/latches.ys
index 3eb550a..fe7887e 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
similarity index 92%
rename from tests/xilinx/logic.ys
rename to tests/arch/xilinx/logic.ys
index 9ae5993..c0f6da3 100644
--- a/tests/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh
new file mode 100644
index 0000000..2272679
--- /dev/null
+++ b/tests/arch/xilinx/macc.sh
@@ -0,0 +1,3 @@
+../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
+iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
+vvp -N ./test_macc
diff --git a/tests/xilinx/macc.v b/tests/arch/xilinx/macc.v
similarity index 100%
rename from tests/xilinx/macc.v
rename to tests/arch/xilinx/macc.v
diff --git a/tests/xilinx/macc.ys b/tests/arch/xilinx/macc.ys
similarity index 100%
rename from tests/xilinx/macc.ys
rename to tests/arch/xilinx/macc.ys
diff --git a/tests/xilinx/macc_tb.v b/tests/arch/xilinx/macc_tb.v
similarity index 100%
rename from tests/xilinx/macc_tb.v
rename to tests/arch/xilinx/macc_tb.v
diff --git a/tests/xilinx/memory.ys b/tests/arch/xilinx/memory.ys
similarity index 92%
rename from tests/xilinx/memory.ys
rename to tests/arch/xilinx/memory.ys
index 5402513..da1ed0e 100644
--- a/tests/xilinx/memory.ys
+++ b/tests/arch/xilinx/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
diff --git a/tests/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
similarity index 91%
rename from tests/xilinx/mul.ys
rename to tests/arch/xilinx/mul.ys
index 66a06ef..d768149 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/xilinx/mul_unsigned.v b/tests/arch/xilinx/mul_unsigned.v
similarity index 100%
rename from tests/xilinx/mul_unsigned.v
rename to tests/arch/xilinx/mul_unsigned.v
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys
similarity index 100%
rename from tests/xilinx/mul_unsigned.ys
rename to tests/arch/xilinx/mul_unsigned.ys
diff --git a/tests/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
similarity index 97%
rename from tests/xilinx/mux.ys
rename to tests/arch/xilinx/mux.ys
index 420dece..821d0fa 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys
similarity index 100%
rename from tests/xilinx/pmgen_xilinx_srl.ys
rename to tests/arch/xilinx/pmgen_xilinx_srl.ys
diff --git a/tests/anlogic/run-test.sh b/tests/arch/xilinx/run-test.sh
similarity index 74%
copy from tests/anlogic/run-test.sh
copy to tests/arch/xilinx/run-test.sh
index 46716f9..bf19b88 100755
--- a/tests/anlogic/run-test.sh
+++ b/tests/arch/xilinx/run-test.sh
@@ -6,7 +6,7 @@
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys
similarity index 91%
rename from tests/xilinx/shifter.ys
rename to tests/arch/xilinx/shifter.ys
index 84e16f4..455437f 100644
--- a/tests/xilinx/shifter.ys
+++ b/tests/arch/xilinx/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys
similarity index 93%
rename from tests/xilinx/tribuf.ys
rename to tests/arch/xilinx/tribuf.ys
index c9cfb85..4697703 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/arch/xilinx/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf
diff --git a/tests/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v
similarity index 100%
rename from tests/xilinx/xilinx_srl.v
rename to tests/arch/xilinx/xilinx_srl.v
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/arch/xilinx/xilinx_srl.ys
similarity index 100%
rename from tests/xilinx/xilinx_srl.ys
rename to tests/arch/xilinx/xilinx_srl.ys
diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/ecp5/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v
deleted file mode 100644
index 223b52d..0000000
--- a/tests/ecp5/adffs.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/ecp5/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/ecp5/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/ecp5/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule
diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/ecp5/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/ecp5/logic.v b/tests/ecp5/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/ecp5/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/ecp5/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v
deleted file mode 100644
index d5b48b1..0000000
--- a/tests/ecp5/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v
deleted file mode 100644
index 782424a..0000000
--- a/tests/ecp5/mux.v
+++ /dev/null
@@ -1,66 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh
deleted file mode 100755
index 46716f9..0000000
--- a/tests/ecp5/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v
deleted file mode 100644
index 04ae49d..0000000
--- a/tests/ecp5/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end
-
-endmodule
diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v
deleted file mode 100644
index 90dd314..0000000
--- a/tests/ecp5/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
diff --git a/tests/efinix/add_sub.v b/tests/efinix/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/efinix/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v
deleted file mode 100644
index 223b52d..0000000
--- a/tests/efinix/adffs.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
diff --git a/tests/efinix/counter.v b/tests/efinix/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/efinix/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/efinix/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/efinix/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule
diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/efinix/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/efinix/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v
deleted file mode 100644
index 5634d65..0000000
--- a/tests/efinix/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [8:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v
deleted file mode 100644
index 27bc0bf..0000000
--- a/tests/efinix/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh
deleted file mode 100755
index 46716f9..0000000
--- a/tests/efinix/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v
deleted file mode 100644
index ce2c81d..0000000
--- a/tests/efinix/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out << 1;
-		out[7] <= in;
-	end
-
-endmodule
diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v
deleted file mode 100644
index c644682..0000000
--- a/tests/efinix/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output reg o;
-    
-    always @(en or i)
-		o <= (en)? i : 1'bZ;
-endmodule
diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/ice40/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
deleted file mode 100644
index 09dc360..0000000
--- a/tests/ice40/adffs.v
+++ /dev/null
@@ -1,87 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge pre )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk, negedge pre )
-		if ( !pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
deleted file mode 100644
index 548060b..0000000
--- a/tests/ice40/adffs.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog adffs.v
-proc
-flatten
-equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNS
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFS
-select -assert-count 2 t:SB_LUT4
-select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v
deleted file mode 100644
index f82cc2e..0000000
--- a/tests/ice40/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys
deleted file mode 100644
index bd859ef..0000000
--- a/tests/ice40/alu.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 62 t:SB_CARRY
-select -assert-count 32 t:SB_DFF
-select -assert-count 655 t:SB_LUT4
-select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/ice40/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v
deleted file mode 100644
index d97840c..0000000
--- a/tests/ice40/dffs.v
+++ /dev/null
@@ -1,37 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
deleted file mode 100644
index ee7f884..0000000
--- a/tests/ice40/dffs.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog dffs.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v
deleted file mode 100644
index 64a3670..0000000
--- a/tests/ice40/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
deleted file mode 100644
index 821d6c3..0000000
--- a/tests/ice40/div_mod.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 59 t:SB_LUT4
-select -assert-count 41 t:SB_CARRY
-select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v
deleted file mode 100644
index 0605bd1..0000000
--- a/tests/ice40/fsm.v
+++ /dev/null
@@ -1,73 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
-endmodule
diff --git a/tests/ice40/latches.v b/tests/ice40/latches.v
deleted file mode 100644
index 9dc43e4..0000000
--- a/tests/ice40/latches.v
+++ /dev/null
@@ -1,58 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
deleted file mode 100644
index 708734e..0000000
--- a/tests/ice40/latches.ys
+++ /dev/null
@@ -1,12 +0,0 @@
-read_verilog latches.v
-
-proc
-flatten
-# Can't run any sort of equivalence check because latches are blown to LUTs
-#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-
-#design -load preopt
-synth_ice40
-cd top
-select -assert-count 4 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/ice40/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/ice40/memory.v b/tests/ice40/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/ice40/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v
deleted file mode 100644
index d5b48b1..0000000
--- a/tests/ice40/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/ice40/mux.v b/tests/ice40/mux.v
deleted file mode 100644
index 0814b73..0000000
--- a/tests/ice40/mux.v
+++ /dev/null
@@ -1,100 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
deleted file mode 100644
index 182b494..0000000
--- a/tests/ice40/mux.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog mux.v
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 19 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
deleted file mode 100755
index 46716f9..0000000
--- a/tests/ice40/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v
deleted file mode 100644
index c556325..0000000
--- a/tests/ice40/shifter.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-`ifndef BUG
-		out    <= out >> 1;
-		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
-	end
-
-endmodule
diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v
deleted file mode 100644
index 870a025..0000000
--- a/tests/ice40/tribuf.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
deleted file mode 100644
index d1e1b31..0000000
--- a/tests/ice40/tribuf.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog tribuf.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/xilinx/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
deleted file mode 100644
index 223b52d..0000000
--- a/tests/xilinx/adffs.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/xilinx/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/xilinx/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/xilinx/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/xilinx/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/xilinx/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/xilinx/macc.sh b/tests/xilinx/macc.sh
deleted file mode 100644
index 86e4c2b..0000000
--- a/tests/xilinx/macc.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
-iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v
-vvp -N ./test_macc
diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/xilinx/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v
deleted file mode 100644
index d5b48b1..0000000
--- a/tests/xilinx/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
deleted file mode 100644
index 27bc0bf..0000000
--- a/tests/xilinx/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
deleted file mode 100755
index 46716f9..0000000
--- a/tests/xilinx/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
deleted file mode 100644
index 04ae49d..0000000
--- a/tests/xilinx/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end
-
-endmodule
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
deleted file mode 100644
index c644682..0000000
--- a/tests/xilinx/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output reg o;
-    
-    always @(en or i)
-		o <= (en)? i : 1'bZ;
-endmodule