diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index cf27d23..b21b0de 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -34,7 +34,6 @@
 	RTLIL::Design *design;
 	RTLIL::Module *module;
 	SigMap sigmap;
-	std::map<RTLIL::SigBit, RTLIL::SigBit> replace_const;
 
 	bool copy_mode;
 	bool hidden_mode;
@@ -231,7 +230,9 @@
 				if (new_wire->port_id > 0) {
 					// Prevents "ERROR: Mismatch in directionality ..." when flattening
 					if (new_wire->port_output)
-						old_sig.replace(replace_const);
+						for (auto &b : old_sig)
+							if (!b.wire)
+								b = module->addWire(NEW_ID);
 					new_cell->setPort(new_wire->name, old_sig);
 				}
 			}
@@ -265,11 +266,6 @@
 			if (wire->port_output)
 				sigmap.add(wire);
 		}
-		auto wire = module->addWire(NEW_ID);
-		replace_const.emplace(State::S0, wire);
-		replace_const.emplace(State::S1, wire);
-		replace_const.emplace(State::Sx, wire);
-		replace_const.emplace(State::Sz, wire);
 
 		if (opt_name.empty())
 		{
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 606bda5..239937f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,6 +538,7 @@
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
+				run("clean");
 				run("clkpart -unpart clkpart");
 			}
 			else {
@@ -545,8 +546,8 @@
 					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 				else
 					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				run("clean");
 			}
-			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming