diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 839f856..211f961 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -175,7 +175,7 @@
 			new_wire->port_output = new_wire_port_output;
 			new_wire->start_offset = wire->start_offset;
 			new_wire->attributes = wire->attributes;
-			if (new_wire->port_output) {
+			if (!flags.is_int_driven.is_fully_zero()) {
 				new_wire->attributes.erase(ID(init));
 				auto sig = sigmap(wire);
 				for (int i = 0; i < GetSize(sig); i++) {
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 239937f..df7514f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,16 +538,14 @@
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
-				run("clean");
-				run("clkpart -unpart clkpart");
 			}
 			else {
 				if (nowidelut)
 					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 				else
 					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-				run("clean");
 			}
+			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
@@ -565,6 +563,9 @@
 		}
 
 		if (check_label("finalize")) {
+			if (help_mode || abc9)
+				run("clkpart -unpart clkpart", "(only if 'abc9')");
+
 			bool do_iopad = iopad || (ise && !noiopad);
 			if (help_mode || !noclkbuf) {
 				if (help_mode || do_iopad)