)]}'
{
  "id": "0ecdf61942245810f0663fc674da99ad96e44713",
  "repo": "third_party/yosys",
  "revision": "f5804a84fd6d9b7d4d50529fcb5c46e3dde89086",
  "path": "manual/APPNOTE_010_Verilog_to_BLIF.tex"
}
