)]}'
{
  "commit": "f6ff311a1dc9876911594328350e2d3fc62a5535",
  "tree": "a1a5aa06a6c361222c3a880c408b2d31ab691818",
  "parents": [
    "7ea0a5937ba2572f6d9d62e73e24df480c49561d"
  ],
  "author": {
    "name": "Clifford Wolf",
    "email": "clifford@clifford.at",
    "time": "Wed Nov 20 12:54:10 2019 +0100"
  },
  "committer": {
    "name": "Clifford Wolf",
    "email": "clifford@clifford.at",
    "time": "Wed Nov 20 12:54:10 2019 +0100"
  },
  "message": "Do not rename VHDL entities to \"entity(impl)\" when they are top modules\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n",
  "tree_diff": [
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    },
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}