diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 552fd4e..9d7dabd 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -15,6 +15,7 @@
 design -save gold
 
 submod
+check -assert
 design -stash gate
 
 design -import gold -as gold
@@ -41,6 +42,7 @@
 design -save gold
 
 submod
+check -assert top
 design -stash gate
 
 design -import gold -as gold
@@ -51,6 +53,35 @@
 
 
 design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] b, c);
+(* submod="bar" *) sub s1(a, b[0]);
+(* submod="bar" *) sub s2(a, c[1]);
+assign c = b;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+
+submod
+check -assert top
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+
+design -reset
 read_verilog -icells <<EOT
 module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
 (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));