diff --git a/CHANGELOG b/CHANGELOG
index a49c27b..d0ac03a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -53,6 +53,7 @@
     - Added "check -mapped"
     - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
+    - Added support for SystemVerilog wildcard port connections (.*)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------
diff --git a/README.md b/README.md
index e469715..58bbc35 100644
--- a/README.md
+++ b/README.md
@@ -376,6 +376,10 @@
   according to the type of the always. These are checked for correctness in
   ``proc_dlatch``.
 
+- The cell attribute ``wildcard_port_conns`` represents wildcard port
+  connections (SystemVerilog ``.*``). These are resolved to concrete
+  connections to matching wires in ``hierarchy``.  
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset