)]}'
{
  "commit": "d8c025184152be36b91449f18087ba40144d4880",
  "tree": "01dd3ec3f2681c41d22803729ba455d457c60075",
  "parents": [
    "6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d"
  ],
  "author": {
    "name": "Marcin Kościelnicki",
    "email": "marcin@symbioticeda.com",
    "time": "Thu Nov 21 06:30:06 2019 +0100"
  },
  "committer": {
    "name": "Marcin Kościelnicki",
    "email": "koriakin@0x04.net",
    "time": "Mon Nov 25 21:34:32 2019 +0100"
  },
  "message": "xilinx: Improve flip-flop handling.\n\nThis adds support for infering more kinds of flip-flops:\n\n- FFs with async set/reset and clock enable\n- FFs with sync set/reset\n- FFs with sync set/reset and clock enable\n\nSome passes have been moved (and some added) in order for dff2dffs to\nwork correctly.\n\nThis gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop\ncapabilities (though not latch capabilities).  Older FPGAs also support\nhaving both a set and a reset input, which will be handled at a later\ndata.\n",
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