tree 01dd3ec3f2681c41d22803729ba455d457c60075
parent 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d
author Marcin Kościelnicki <marcin@symbioticeda.com> 1574314206 +0100
committer Marcin Kościelnicki <koriakin@0x04.net> 1574714072 +0100

xilinx: Improve flip-flop handling.

This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.