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foss-fpga-tools / third_party / yosys / refs/heads/mwk/xilinx-dsp48-sim / . / techlibs / xilinx
tree: 19cce4d6c6dcb0f62dab2d62bf2540dca8114884 [path history] [tgz]
  1. tests/
  2. .gitignore
  3. abc9_map.v
  4. abc9_model.v
  5. abc9_unmap.v
  6. abc9_xc7.box
  7. abc9_xc7.lut
  8. abc9_xc7_nowide.lut
  9. arith_map.v
  10. brams_init.py
  11. cells_map.v
  12. cells_sim.v
  13. cells_xtra.py
  14. cells_xtra.v
  15. lut_map.v
  16. lutrams.txt
  17. lutrams_map.v
  18. Makefile.inc
  19. mux_map.v
  20. synth_xilinx.cc
  21. xc3s_mult_map.v
  22. xc3sda_dsp_map.v
  23. xc4v_dsp_map.v
  24. xc5v_dsp_map.v
  25. xc6s_brams.txt
  26. xc6s_brams_map.v
  27. xc6s_dsp_map.v
  28. xc6s_ff_map.v
  29. xc7_brams_map.v
  30. xc7_dsp_map.v
  31. xc7_ff_map.v
  32. xc7_xcu_brams.txt
  33. xcu_brams_map.v
  34. xcu_dsp_map.v
  35. xcup_urams.txt
  36. xcup_urams_map.v