)]}'
{
  "id": "c2d52969f52dc7159127e478016329ea0e13b6fe",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "aadbcdcdd51512e5917e74772f92ba667c81ac0f",
      "name": ".gitignore"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dbaace5854c9762a5d673274e5a1db2c7b52fa71",
      "name": "Makefile.inc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7848c626d58cdbfcb23a8084ae4b24c8dfd05189",
      "name": "const2ast.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dea22ee8a946f482d3a391f4570b9aab58778f67",
      "name": "preproc.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "aeea36a2b7e24289690e032be22ada374b229d54",
      "name": "verilog_frontend.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "523bbc89786defa4166302fda5c405850ca476d6",
      "name": "verilog_frontend.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f9118e1421e4566705f0234cd0e54f3553551239",
      "name": "verilog_lexer.l"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "a6718b02005a42fe79755f4078ccd15de83efe09",
      "name": "verilog_parser.y"
    }
  ]
}