)]}'
{
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        "time": "Fri Nov 29 17:33:41 2019 +0100"
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        "time": "Fri Nov 29 17:33:41 2019 +0100"
      },
      "message": "Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll\n\nxilinx: Add missing blackbox cell for BUFPLL."
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        "time": "Fri Nov 29 16:56:27 2019 +0100"
      },
      "message": "xilinx: Add missing blackbox cell for BUFPLL.\n"
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        "time": "Wed Nov 27 21:55:56 2019 -0800"
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        "email": "eddie@fpgeh.com",
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 22:59:05 2019 -0800"
      },
      "message": "latch -\u003e box\n"
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        "time": "Tue Nov 26 22:51:16 2019 -0800"
      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 22:51:16 2019 -0800"
      },
      "message": "Add citation\n"
    },
    {
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        "email": "eddie@fpgeh.com",
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      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 22:51:00 2019 -0800"
      },
      "message": "Check for either sign or zero extension for postAdd packing\n"
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 22:41:35 2019 -0800"
      },
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    },
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      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 21:57:50 2019 -0800"
      },
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      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 21:57:50 2019 -0800"
      },
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        "email": "eddie@fpgeh.com",
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      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 21:55:37 2019 -0800"
      },
      "message": "xaiger: do not promote output wires\n"
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        "email": "eddie@fpgeh.com",
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      },
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        "email": "eddie@fpgeh.com",
        "time": "Tue Nov 26 21:26:30 2019 -0800"
      },
      "message": "Add testcase derived from fastfir_dynamictaps benchmark\n"
    },
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      },
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        "email": "mwk@0x04.net",
        "time": "Tue Nov 26 08:15:20 2019 +0100"
      },
      "message": "xilinx: Add simulation models for IOBUF and OBUFT.\n"
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        "time": "Mon Nov 25 20:40:39 2019 +0100"
      },
      "message": "clkbufmap: Add support for inverters in clock path.\n"
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        "email": "mwk@0x04.net",
        "time": "Mon Nov 25 20:40:39 2019 +0100"
      },
      "message": "xilinx: Use INV instead of LUT1 when applicable\n"
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        "time": "Fri Nov 22 22:45:40 2019 -0800"
      },
      "message": "Merge pull request #1520 from pietrmar/fix-1463\n\ncoolrunner2: remove spurious log_pop() call, fixes #1463"
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        "email": "martin@pietryka.at",
        "time": "Sat Nov 23 06:21:40 2019 +0100"
      },
      "message": "coolrunner2: remove spurious log_pop() call, fixes #1463\n\nThis was causing a segmentation fault because there is no accompanying\nlog_push() call so header_count.size() became -1.\n\nSigned-off-by: Martin Pietryka \u003cmartin@pietryka.at\u003e\n"
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        "time": "Fri Nov 22 18:11:58 2019 +0100"
      },
      "message": "Merge pull request #1517 from YosysHQ/clifford/optmem\n\nAdd \"opt_mem\" pass"
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        "time": "Fri Nov 22 18:10:34 2019 +0100"
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        "email": "noreply@github.com",
        "time": "Fri Nov 22 18:10:34 2019 +0100"
      },
      "message": "Merge pull request #1515 from YosysHQ/clifford/svastuff\n\nAdd Verific/SVA support for \"always\" and \"nexttime\" properties"
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      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Fri Nov 22 17:45:22 2019 +0100"
      },
      "message": "Add \"opt_mem\" pass\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
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    {
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        "time": "Fri Nov 22 16:11:56 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Fri Nov 22 16:11:56 2019 +0100"
      },
      "message": "Add Verific support for SVA nexttime properties\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
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    {
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        "email": "clifford@clifford.at",
        "time": "Fri Nov 22 16:00:07 2019 +0100"
      },
      "message": "Improve handling of verific primitives in \"verific -import -V\" mode\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
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        "time": "Fri Nov 22 15:52:21 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Fri Nov 22 15:52:21 2019 +0100"
      },
      "message": "Add Verific SVA support for \"always\" properties\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d",
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        "time": "Fri Nov 22 15:32:29 2019 +0100"
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        "time": "Fri Nov 22 15:32:29 2019 +0100"
      },
      "message": "Merge pull request #1511 from YosysHQ/dave/always\n\nsv: Error checking for always_comb, always_latch and always_ff"
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        "name": "Marcin Kościelnicki",
        "email": "koriakin@0x04.net",
        "time": "Fri Nov 22 12:15:33 2019 +0100"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "mwk@0x04.net",
        "time": "Fri Nov 22 14:49:35 2019 +0100"
      },
      "message": "gowin: Remove show command from tests.\n"
    },
    {
      "commit": "1d098b719513ef2fa701b88b9b56c6e989384c05",
      "tree": "73e6ae2d03e8094584296e77938f9fc6c316d605",
      "parents": [
        "0ac330bb81946081a3ab9ae45ef5aa7122dcb786"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "koriakin@0x04.net",
        "time": "Fri Nov 22 12:10:57 2019 +0100"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "mwk@0x04.net",
        "time": "Fri Nov 22 14:40:36 2019 +0100"
      },
      "message": "gowin: Add missing .gitignore entries\n"
    },
    {
      "commit": "b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd",
      "tree": "0688eb03bfee098fe585ae789f6448943a765e15",
      "parents": [
        "49b670ca38988bcce453125166528b32e16f7bb4"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Nov 22 12:46:19 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Nov 22 12:46:19 2019 +0000"
      },
      "message": "Update CHANGELOG and README\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "49b670ca38988bcce453125166528b32e16f7bb4",
      "tree": "283a6d0b736723d08a645006c28ee90047045412",
      "parents": [
        "ca99b1ee8dca6d49d79576e19d35111b4ad5ea45"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 21:06:28 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 21:06:28 2019 +0000"
      },
      "message": "sv: Add tests for SV always types\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "ca99b1ee8dca6d49d79576e19d35111b4ad5ea45",
      "tree": "925f428c7a35e663c8f2b56fcb2e83c295a692a5",
      "parents": [
        "9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 20:46:41 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 20:46:41 2019 +0000"
      },
      "message": "proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "9e4801cca7bf346ac4d2ca0feaacda1e4bb27ac2",
      "tree": "9310f511fb6aa2fc61d3660d7271f8cc61f19361",
      "parents": [
        "0ac330bb81946081a3ab9ae45ef5aa7122dcb786"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 20:27:19 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 21 20:27:19 2019 +0000"
      },
      "message": "sv: Correct parsing of always_comb, always_ff and always_latch\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "0ac330bb81946081a3ab9ae45ef5aa7122dcb786",
      "tree": "92b3e480508add4556ca59ac331cac5865169e11",
      "parents": [
        "7ea0a5937ba2572f6d9d62e73e24df480c49561d",
        "55bda2b2c693a7ff79da545e7b52901de00df475"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 20 13:49:27 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Nov 20 13:49:27 2019 +0100"
      },
      "message": "Merge pull request #1507 from YosysHQ/clifford/verificfixes\n\nSome fixes in our Verific integration"
    },
    {
      "commit": "55bda2b2c693a7ff79da545e7b52901de00df475",
      "tree": "92b3e480508add4556ca59ac331cac5865169e11",
      "parents": [
        "f6ff311a1dc9876911594328350e2d3fc62a5535"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 20 12:56:31 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 20 12:56:31 2019 +0100"
      },
      "message": "Correctly treat empty modules as blackboxes in Verific\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "f6ff311a1dc9876911594328350e2d3fc62a5535",
      "tree": "a1a5aa06a6c361222c3a880c408b2d31ab691818",
      "parents": [
        "7ea0a5937ba2572f6d9d62e73e24df480c49561d"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 20 12:54:10 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 20 12:54:10 2019 +0100"
      },
      "message": "Do not rename VHDL entities to \"entity(impl)\" when they are top modules\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "7ea0a5937ba2572f6d9d62e73e24df480c49561d",
      "tree": "7825f438b83fdc730764ba15016eeeac9eb0cf41",
      "parents": [
        "15232a48af60fb7da3c3afdd144882ace2194197",
        "8ab412eb16b1d4f98117247bf85e0c37627ee459"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 19 17:29:27 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Nov 19 17:29:27 2019 +0100"
      },
      "message": "Merge pull request #1449 from pepijndevos/gowin\n\nImprovements for gowin support"
    },
    {
      "commit": "8ab412eb16b1d4f98117247bf85e0c37627ee459",
      "tree": "1adc1c347057751f515518ba780bb5aa2203d263",
      "parents": [
        "dd8c7e1ddda152e9c06d4b950564eb4aa1051c98"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Tue Nov 19 15:53:44 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Tue Nov 19 15:53:44 2019 +0100"
      },
      "message": "Remove dff init altogether\n\nThe hardware does not actually support it.\nIn reality it is always initialised to its reset value.\n"
    },
    {
      "commit": "15232a48af60fb7da3c3afdd144882ace2194197",
      "tree": "9f65f4cf436dd53d1d926ae2bbd85c36433a70ed",
      "parents": [
        "7a9081440c33af05cd5b24b4eb8907ac2ba4876a"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "marcin@symbioticeda.com",
        "time": "Mon Nov 18 08:19:53 2019 +0100"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "mwk@0x04.net",
        "time": "Tue Nov 19 08:57:39 2019 +0100"
      },
      "message": "Fix #1462, #1480.\n"
    },
    {
      "commit": "7a9081440c33af05cd5b24b4eb8907ac2ba4876a",
      "tree": "c4b9467b060b3f7c5b00d36e60db0b69855ec1c8",
      "parents": [
        "9ee3c57e460b15acb8e1503e97fc35aa6eed0661"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "marcin@symbioticeda.com",
        "time": "Mon Nov 18 03:47:56 2019 +0100"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "mwk@0x04.net",
        "time": "Tue Nov 19 01:00:58 2019 +0100"
      },
      "message": "xilinx: Add simulation models for MULT18X18* and DSP48A*.\n\nThis adds simulation models for the following primitives:\n\n- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)\n- MULT18X18SIO (Spartan 3E, Spartan 3A)\n- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1\n- DSP48A1 (Spartan 6)\n"
    },
    {
      "commit": "7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77",
      "tree": "29ee366e0d82b9dae913f896b688ea80b00ec130",
      "parents": [
        "9ee3c57e460b15acb8e1503e97fc35aa6eed0661"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Mon Nov 18 13:58:03 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Mon Nov 18 13:58:03 2019 +0000"
      },
      "message": "memory_collect: Copy attr from RTLIL::Memory to  cell\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "dd8c7e1ddda152e9c06d4b950564eb4aa1051c98",
      "tree": "7711b9488ba7046b197cbb5fc2e9c8c79296f885",
      "parents": [
        "32f0296df1b97ff5b3bcc442ac38f27a786947d6"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 18 14:25:46 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 18 14:26:09 2019 +0100"
      },
      "message": "add help for nowidelut and abc9 options\n"
    },
    {
      "commit": "9ee3c57e460b15acb8e1503e97fc35aa6eed0661",
      "tree": "06999fcbfb9a7f4dbe59b54c03c25e6629a6b0bb",
      "parents": [
        "cdb566b2d6a998ccaf5406f584e3ec810973dff9",
        "38e72d6e13b908007577b7782078ac8b968496f5"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Mon Nov 18 10:53:14 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Nov 18 10:53:14 2019 +0100"
      },
      "message": "Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix\n\nFix #1496."
    },
    {
      "commit": "cdb566b2d6a998ccaf5406f584e3ec810973dff9",
      "tree": "0c507eb7b8383de0d5763b1fca77743c27c1f5f3",
      "parents": [
        "527434de493f88d5da64ae216df3b5a85558e47b",
        "3c643c57dfee9956697e8629a746bc04439be5a2"
      ],
      "author": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Mon Nov 18 09:37:14 2019 +0000"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Nov 18 09:37:14 2019 +0000"
      },
      "message": "Merge pull request #1494 from whitequark/write_verilog-extmem\n\nwrite_verilog: add -extmem option, to write split memory init files"
    },
    {
      "commit": "38e72d6e13b908007577b7782078ac8b968496f5",
      "tree": "41e77080c67c9d35dff693253234471c2f43a941",
      "parents": [
        "527434de493f88d5da64ae216df3b5a85558e47b"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "marcin@symbioticeda.com",
        "time": "Mon Nov 18 04:16:48 2019 +0100"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "marcin@symbioticeda.com",
        "time": "Mon Nov 18 04:16:48 2019 +0100"
      },
      "message": "Fix #1496.\n"
    },
    {
      "commit": "3c643c57dfee9956697e8629a746bc04439be5a2",
      "tree": "3a31940ce7e02c5479ed578fc555fbc7f9d3d97d",
      "parents": [
        "e907ee4fde6fe83faf246dfcc2afb207e20d803d"
      ],
      "author": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Fri Nov 15 03:11:46 2019 +0000"
      },
      "committer": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Mon Nov 18 01:27:21 2019 +0000"
      },
      "message": "write_verilog: add -extmem option, to write split memory init files.\n\nSome toolchains (in particular Quartus) are pathologically slow if\na large amount of assignments in `initial` blocks are used.\n"
    },
    {
      "commit": "527434de493f88d5da64ae216df3b5a85558e47b",
      "tree": "389e66bd56f4fff3b57224c04a9d2fedf0398c96",
      "parents": [
        "51e4e29bb1f7c030b0cac351c522dc41f7587be2",
        "f5804a84fd6d9b7d4d50529fcb5c46e3dde89086"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Sun Nov 17 10:42:30 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sun Nov 17 10:42:30 2019 +0100"
      },
      "message": "Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst\n\nwreduce: Don\u0027t trim zeros or sext when not matching ARST_VALUE"
    },
    {
      "commit": "32f0296df1b97ff5b3bcc442ac38f27a786947d6",
      "tree": "72ec224a90bb5a40e007a88fe37085dcc786a0e0",
      "parents": [
        "ab8c521030a2c91a1e388d6f3c627a7f7dd525b2",
        "51e4e29bb1f7c030b0cac351c522dc41f7587be2"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Sat Nov 16 12:43:17 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Sat Nov 16 12:43:17 2019 +0100"
      },
      "message": "Merge branch \u0027master\u0027 of https://github.com/YosysHQ/yosys into gowin\n"
    },
    {
      "commit": "51e4e29bb1f7c030b0cac351c522dc41f7587be2",
      "tree": "5d1f67b35ee733299369d914e6a03d51a7a17717",
      "parents": [
        "e907ee4fde6fe83faf246dfcc2afb207e20d803d"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Nov 15 21:03:11 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Nov 15 21:03:11 2019 +0000"
      },
      "message": "ecp5: Use new autoname pass for better cell/net names\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "f5804a84fd6d9b7d4d50529fcb5c46e3dde89086",
      "tree": "49eb22bdb4c1c57e184fa02bab999159702272c3",
      "parents": [
        "4b18a4528ba7597bd7437837ab6d34cd8de2e110"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 14 18:43:15 2019 +0000"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Nov 14 18:43:15 2019 +0000"
      },
      "message": "wreduce: Don\u0027t trim zeros or sext when not matching ARST_VALUE\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "e907ee4fde6fe83faf246dfcc2afb207e20d803d",
      "tree": "9dc18a453ce94db834e2dc55e14636e231c43d78",
      "parents": [
        "4b18a4528ba7597bd7437837ab6d34cd8de2e110",
        "07c854b7afc793a589df06c7fce200260378b379"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 18:03:44 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Nov 14 18:03:44 2019 +0100"
      },
      "message": "Merge pull request #1490 from YosysHQ/clifford/autoname\n\nAdd \"autoname\" pass and use it in \"synth_ice40\""
    },
    {
      "commit": "4b18a4528ba7597bd7437837ab6d34cd8de2e110",
      "tree": "046cfd098cee2b4b87429391d9d4bffe626a5ab5",
      "parents": [
        "056ef767111dd1999b171bf3902fbbfb76cf3026",
        "f8f572fbfc4e5de3afa7dc05f5fa1feff87aabd3"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 12:10:12 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Nov 14 12:10:12 2019 +0100"
      },
      "message": "Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams\n\nPython Wrappers: Expose global variables and allow logging to python streams"
    },
    {
      "commit": "056ef767111dd1999b171bf3902fbbfb76cf3026",
      "tree": "23047a0a2bbed927dd3efa85d8112938aed77194",
      "parents": [
        "f453f579bff2c6c64357c6482ad132f84f715fff",
        "e135ed5d809ae97b0d4d25ff454456aea44af8fc"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 12:07:25 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Nov 14 12:07:25 2019 +0100"
      },
      "message": "Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim\n\nice40: Support for post-place-and-route timing simulations"
    },
    {
      "commit": "f453f579bff2c6c64357c6482ad132f84f715fff",
      "tree": "2b393a693d327e7efcaa95fae734a5b2ff2e1979",
      "parents": [
        "ab0fb19cfff7760bfd69b49ed6d81a823be2a6ba",
        "cd44826d5026316d9b44ae33c1fcf0d8faf550c4"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:57:53 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:57:53 2019 +0100"
      },
      "message": "Merge branch \u0027makaimann-label-bads-btor\u0027\n"
    },
    {
      "commit": "cd44826d5026316d9b44ae33c1fcf0d8faf550c4",
      "tree": "2b393a693d327e7efcaa95fae734a5b2ff2e1979",
      "parents": [
        "89834b98f7715b131193f8283f09d665b9290eff"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:57:38 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:57:38 2019 +0100"
      },
      "message": "Use cell name for btor bad state props when it is a public name\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "89834b98f7715b131193f8283f09d665b9290eff",
      "tree": "3830defbea85a6d26e377f42693fec47e1d4326a",
      "parents": [
        "ab0fb19cfff7760bfd69b49ed6d81a823be2a6ba",
        "d88cc139a029764cf62d95b2eaaff99e270a134a"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:52:41 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 14 11:52:41 2019 +0100"
      },
      "message": "Merge branch \u0027label-bads-btor\u0027 of https://github.com/makaimann/yosys into makaimann-label-bads-btor\n"
    },
    {
      "commit": "07c854b7afc793a589df06c7fce200260378b379",
      "tree": "b5a5471c6ea60444b80076e7cf1cd5eaa4affb53",
      "parents": [
        "6e332161dbdc399c41041cebaf83cbb156b331a7"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 13 13:41:16 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 13 13:41:16 2019 +0100"
      },
      "message": "Add \"autoname\" pass and use it in \"synth_ice40\"\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "ab0fb19cfff7760bfd69b49ed6d81a823be2a6ba",
      "tree": "0829cab4f0acb568903c5a34733adce1957a4036",
      "parents": [
        "6e332161dbdc399c41041cebaf83cbb156b331a7",
        "c68722818a09ce541c380178ff17e548db9c897d"
      ],
      "author": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Wed Nov 13 11:57:17 2019 +0000"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Nov 13 11:57:17 2019 +0000"
      },
      "message": "Merge pull request #1488 from whitequark/flowmap-fixes\n\nflowmap: fix a few crashes"
    },
    {
      "commit": "6e332161dbdc399c41041cebaf83cbb156b331a7",
      "tree": "3f4f2ea5b501233b2d97d8b7b5491fa69ececb56",
      "parents": [
        "e0ba78bdf2d65ace45be575de6a1cc43baae7f22",
        "4be5a0fd7c1573f81c6c70a16601f7ce5ab87210"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Nov 13 12:34:27 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Nov 13 12:34:27 2019 +0100"
      },
      "message": "Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix\n\nBugfix in fsm_detect"
    },
    {
      "commit": "4be5a0fd7c1573f81c6c70a16601f7ce5ab87210",
      "tree": "3f4f2ea5b501233b2d97d8b7b5491fa69ececb56",
      "parents": [
        "16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 12 17:31:30 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 12 17:31:30 2019 +0100"
      },
      "message": "Update fsm_detect bugfix\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856",
      "tree": "1673ad40ddcb8265493f79c776535cff9d9c00c0",
      "parents": [
        "e0ba78bdf2d65ace45be575de6a1cc43baae7f22"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 12 14:26:02 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 12 14:26:02 2019 +0100"
      },
      "message": "Bugfix in fsm_detect\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "e0ba78bdf2d65ace45be575de6a1cc43baae7f22",
      "tree": "b518fa47c9a27aa37da0deceb66313d769e14c7c",
      "parents": [
        "1d148491c5a9b816297c08e5ea3a98ff0bd3623d",
        "3e0ffe05a79d3196b3644cddf422edb927673b04"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Nov 12 10:24:12 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Nov 12 10:24:12 2019 +0100"
      },
      "message": "Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne\n\nDo not map $eq and $ne in cmp2lut, only proper arithmetic cmp"
    },
    {
      "commit": "d88cc139a029764cf62d95b2eaaff99e270a134a",
      "tree": "d80af0f289c5350a62ea32db34e129af64b2d57e",
      "parents": [
        "1d148491c5a9b816297c08e5ea3a98ff0bd3623d"
      ],
      "author": {
        "name": "Makai Mann",
        "email": "makaim@stanford.edu",
        "time": "Mon Nov 11 16:40:51 2019 -0800"
      },
      "committer": {
        "name": "Makai Mann",
        "email": "makaim@stanford.edu",
        "time": "Mon Nov 11 16:40:51 2019 -0800"
      },
      "message": "Add an info string symbol for bad states in btor backend\n"
    },
    {
      "commit": "c68722818a09ce541c380178ff17e548db9c897d",
      "tree": "a1c1731e4dc90043e22cbcd342bdd630e2fbeae3",
      "parents": [
        "eef32195bd1afb4f029bf3039377e65f0beabac2"
      ],
      "author": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Tue Nov 12 00:15:43 2019 +0000"
      },
      "committer": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Tue Nov 12 00:15:43 2019 +0000"
      },
      "message": "flowmap: when doing mincut, ensure source is always in X, not X̅.\n\nFixes #1475.\n"
    },
    {
      "commit": "eef32195bd1afb4f029bf3039377e65f0beabac2",
      "tree": "c5733037bca86b1065a86f6e1f8eb2662797ab50",
      "parents": [
        "1d148491c5a9b816297c08e5ea3a98ff0bd3623d"
      ],
      "author": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Mon Nov 11 23:13:00 2019 +0000"
      },
      "committer": {
        "name": "whitequark",
        "email": "whitequark@whitequark.org",
        "time": "Mon Nov 11 23:13:00 2019 +0000"
      },
      "message": "flowmap: don\u0027t break if that creates a k+2 (and larger) LUT either.\n\nFixes #1405.\n"
    },
    {
      "commit": "ab8c521030a2c91a1e388d6f3c627a7f7dd525b2",
      "tree": "d48eb9f4b093113008d46a5bf2dc004d7143a943",
      "parents": [
        "ec3faa7b967564dabdd465267657def86846b259"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 11 17:51:26 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 11 17:51:26 2019 +0100"
      },
      "message": "fix fsm test with proper clock enable polarity\n"
    },
    {
      "commit": "ec3faa7b967564dabdd465267657def86846b259",
      "tree": "a0e6b31ff0fb94e54260a078900144a30b20804f",
      "parents": [
        "0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1",
        "1d148491c5a9b816297c08e5ea3a98ff0bd3623d"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 11 17:08:40 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Nov 11 17:08:40 2019 +0100"
      },
      "message": "Merge branch \u0027master\u0027 of https://github.com/YosysHQ/yosys into gowin\n"
    },
    {
      "commit": "3e0ffe05a79d3196b3644cddf422edb927673b04",
      "tree": "b518fa47c9a27aa37da0deceb66313d769e14c7c",
      "parents": [
        "362f4f996d49cca4be240d5c96fba013dd56a8cb"
      ],
      "author": {
        "name": "Miodrag Milanovic",
        "email": "mmicko@gmail.com",
        "time": "Mon Nov 11 15:41:33 2019 +0100"
      },
      "committer": {
        "name": "Miodrag Milanovic",
        "email": "mmicko@gmail.com",
        "time": "Mon Nov 11 15:41:33 2019 +0100"
      },
      "message": "Fixed tests\n"
    },
    {
      "commit": "362f4f996d49cca4be240d5c96fba013dd56a8cb",
      "tree": "4428788f8deeff38461e570884bd7f058fa8c828",
      "parents": [
        "1d148491c5a9b816297c08e5ea3a98ff0bd3623d"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Mon Nov 11 15:07:29 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Mon Nov 11 15:07:29 2019 +0100"
      },
      "message": "Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "1d148491c5a9b816297c08e5ea3a98ff0bd3623d",
      "tree": "991daa0f8b9703a57ecd5e8959fbc2d51dcec366",
      "parents": [
        "65f197e28f789aa6bcfd8f4841c0e1ebb91b99a8",
        "c3ad37520044d3de12fd1b3acc723cca75c3bb94"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Sun Nov 10 11:00:38 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sun Nov 10 11:00:38 2019 +0100"
      },
      "message": "Merge pull request #1470 from YosysHQ/clifford/subpassdoc\n\nAdd CodingReadme section on script passes"
    },
    {
      "commit": "65f197e28f789aa6bcfd8f4841c0e1ebb91b99a8",
      "tree": "2e188e433c4cfdf52fa41e879b7140a8260c9970",
      "parents": [
        "c4bd318e76240d3e6a95109c19641cdfd86517b8"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 07 13:30:03 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Nov 07 13:30:03 2019 +0100"
      },
      "message": "Add check for valid macro names in macro definitions\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1",
      "tree": "551985ca52e16aa63ebd869df7ed6dec0d78717f",
      "parents": [
        "df8390f5df9868b583ce88a4d2ce41511fab2f7b"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Wed Nov 06 19:48:18 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Wed Nov 06 19:48:18 2019 +0100"
      },
      "message": "fix wide luts\n"
    },
    {
      "commit": "c4bd318e76240d3e6a95109c19641cdfd86517b8",
      "tree": "652f7209fd5b65045084914b04f98fbbaecede3e",
      "parents": [
        "5110a34dd74bc96c47d4aef47bc155110de2d87e"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "koriakin@0x04.net",
        "time": "Fri Nov 01 14:00:15 2019 +0000"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "mwk@0x04.net",
        "time": "Wed Nov 06 15:11:27 2019 +0100"
      },
      "message": "synth_xilinx: Merge blackbox primitive libraries.\n\nFirst, there are no longer separate cell libraries for xc6s/xc7/xcu.\nManually instantiating a primitive for a \"wrong\" family will result\nin yosys passing it straight through to the output, and it will be\neither upgraded or rejected by the P\u0026R tool.\n\nSecond, the blackbox library is expanded to cover many more families:\neverything from Spartan 3 up is included.  Primitives for Virtex and\nVirtex 2 are listed in the Python file as well if we ever want to\ninclude them, but that would require having two different ISE versions\n(10.1 and 14.7) available when running cells_xtra.py, and so is probably\nmore trouble than it\u0027s worth.\n\nThird, the blockram blackboxes are no longer in separate files — there\nis no practical reason to do so (from synthesis PoV, they are no\ndifferent from any other cells_xtra blackbox), and they needlessly\ncomplicated the flow (among other things, merging them allows the user\nto use eg. Series 7 primitives and have them auto-upgraded to\nUltrascale).\n\nLast, since xc5v logic synthesis appears to work reasonably well\n(the only major problem is lack of blockram inference support), xc5v is\nnow an accepted setting for the -family option.\n"
    },
    {
      "commit": "5110a34dd74bc96c47d4aef47bc155110de2d87e",
      "tree": "530d82f073ee9c4858f666b91e7bf2a7a9fca3bb",
      "parents": [
        "81876a3734dacde199446343ce338b24e9b2796f"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Mon Nov 04 14:25:13 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Mon Nov 04 14:25:13 2019 +0100"
      },
      "message": "Fix write_aiger bug added in 524af21\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "c3ad37520044d3de12fd1b3acc723cca75c3bb94",
      "tree": "0f3bed36ac4ac80df8f8ebd6b4764be41be90f60",
      "parents": [
        "81876a3734dacde199446343ce338b24e9b2796f"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 31 10:46:20 2019 +0100"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 31 10:46:20 2019 +0100"
      },
      "message": "Add CodingReadme section on script passes\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "df8390f5df9868b583ce88a4d2ce41511fab2f7b",
      "tree": "55088678a5ae2860f6ab39b9e6be3f7bcdc18d05",
      "parents": [
        "0f6269b04c4a5f44b62021759507bcbe61a7c8d7"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Wed Oct 30 14:58:25 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Wed Oct 30 14:58:25 2019 +0100"
      },
      "message": "don\u0027t cound exact luts in big muxes; futile and fragile\n"
    },
    {
      "commit": "0f6269b04c4a5f44b62021759507bcbe61a7c8d7",
      "tree": "17f1fb8a1e4532045c86cbb7151fc15a02481be2",
      "parents": [
        "903f9973913371452005eb173ac50fec1d5d1447"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 15:33:05 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 15:33:05 2019 +0100"
      },
      "message": "add IOBUF\n"
    },
    {
      "commit": "903f9973913371452005eb173ac50fec1d5d1447",
      "tree": "b160b35c7a1048dc5d1ef2f63a6159f5aef6fe1f",
      "parents": [
        "9517525224c7bc4b8ac7d093066485888a337b76"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 15:18:01 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 15:18:01 2019 +0100"
      },
      "message": "add tristate buffer and test\n"
    },
    {
      "commit": "9517525224c7bc4b8ac7d093066485888a337b76",
      "tree": "6dd3f81a447565eb4fbcdecaaf52ab0fcd09437b",
      "parents": [
        "4ec4d5ec7e6c70c50c513de93c1d478ff76d8298"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 14:40:12 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 14:40:12 2019 +0100"
      },
      "message": "do not use wide luts in testcase\n"
    },
    {
      "commit": "4ec4d5ec7e6c70c50c513de93c1d478ff76d8298",
      "tree": "977dab5a2978f71484e0b8a1aa5dc2dfb29345d9",
      "parents": [
        "2f5e9e9885df0011a3b70b0ab64f54fcd33ce347"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 14:28:03 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 14:28:03 2019 +0100"
      },
      "message": "actually run the gowin tests\n"
    },
    {
      "commit": "2f5e9e9885df0011a3b70b0ab64f54fcd33ce347",
      "tree": "c7267494b72935d11e4bcba898cb801a6a0154f3",
      "parents": [
        "c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 13:10:12 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 13:10:12 2019 +0100"
      },
      "message": "More formatting\n"
    },
    {
      "commit": "c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c",
      "tree": "4c60a380774bd3535db5da20f5a7b5ead815041a",
      "parents": [
        "293b2c2de5c127d860d9ce0c7ac98908fa053520"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 13:01:20 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 13:01:20 2019 +0100"
      },
      "message": "really really fix formatting maybe\n"
    },
    {
      "commit": "293b2c2de5c127d860d9ce0c7ac98908fa053520",
      "tree": "d1fe7ccfa5b6c095821ceaaca51c8eaf99c5db6e",
      "parents": [
        "f88335a8a5284a8e69230ec20eeeca6c02b055bf"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 12:57:12 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 12:57:12 2019 +0100"
      },
      "message": "undo formatting fuckup\n"
    },
    {
      "commit": "f88335a8a5284a8e69230ec20eeeca6c02b055bf",
      "tree": "2eeb2876fd7eb9fcae6216c72ac940fac94bea6c",
      "parents": [
        "5fad53b504a7ac05fb959f0ca84829bd550aac47"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 12:49:08 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 12:49:08 2019 +0100"
      },
      "message": "add wide luts\n"
    },
    {
      "commit": "5fad53b504a7ac05fb959f0ca84829bd550aac47",
      "tree": "a52919869c46da49af4c277c45307b6b04c7286a",
      "parents": [
        "8226f2db0b65dffb59c4420de96dccd2e0be36ed"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 10:33:27 2019 +0100"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 28 10:33:27 2019 +0100"
      },
      "message": "add 32-bit BRAM and byte-enables\n"
    },
    {
      "commit": "81876a3734dacde199446343ce338b24e9b2796f",
      "tree": "f637930db9d29efaeb4609017f07761f012b6d99",
      "parents": [
        "84982b308343315c889d3d00116db820a51cad78",
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      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Sun Oct 27 10:25:01 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sun Oct 27 10:25:01 2019 +0100"
      },
      "message": "Merge pull request #1393 from whitequark/write_verilog-avoid-init\n\nwrite_verilog: do not print (*init*) attributes on regs"
    },
    {
      "commit": "8226f2db0b65dffb59c4420de96dccd2e0be36ed",
      "tree": "d4ae8d996ea87c741b454c7609d8b1b9fe5424c6",
      "parents": [
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      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Thu Oct 24 13:39:43 2019 +0200"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Thu Oct 24 13:39:43 2019 +0200"
      },
      "message": "ALU sim tweaks\n"
    },
    {
      "commit": "84982b308343315c889d3d00116db820a51cad78",
      "tree": "9eabe561c9a24e57bddff83886e996c015bd3e3c",
      "parents": [
        "34dadd9ab20494057c1ac7dae443b48eee0c2c30"
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      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 24 12:13:37 2019 +0200"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 24 12:13:50 2019 +0200"
      },
      "message": "Improve naming scheme for (VHDL) modules imported from Verific\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "34dadd9ab20494057c1ac7dae443b48eee0c2c30",
      "tree": "f413785a96c0b168e1275c44c6995067bc7f6d18",
      "parents": [
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      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Thu Oct 24 08:14:20 2019 +0100"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Oct 24 08:14:20 2019 +0100"
      },
      "message": "Merge pull request #1455 from YosysHQ/dave/ultrascaleplus\n\nAdd BRAM and URAM mapping for UltraScale[+]"
    },
    {
      "commit": "d49c6b2cba0256573352ae4dd5669e94ef75b60e",
      "tree": "6ebe15eb7b1ae31dd0e03d548f426ced76ec2ca7",
      "parents": [
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      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 24 09:14:03 2019 +0200"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Thu Oct 24 09:14:03 2019 +0200"
      },
      "message": "Add \"verific -L\"\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "e135ed5d809ae97b0d4d25ff454456aea44af8fc",
      "tree": "17c19982cc615e2fb3b68f2336e56acd513a75c3",
      "parents": [
        "37dd3ad3fe434243303e11c22831579569324def"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Wed Oct 23 18:44:34 2019 +0100"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Wed Oct 23 18:44:34 2019 +0100"
      },
      "message": "ice40: Add post-pnr ICESTORM_RAM model and fix FFs\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "37dd3ad3fe434243303e11c22831579569324def",
      "tree": "3d583847ad6d5047af959dc4aeba7d7f416cf5da",
      "parents": [
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      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Sun Oct 20 10:24:47 2019 +0100"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Wed Oct 23 12:03:31 2019 +0100"
      },
      "message": "ice40: Support for post-pnr timing simulation\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "3506eaf2904cddf5132c598a527e050a79a181d5",
      "tree": "c5909467e7a42fa6b69b0e49d440a787bc36e3c5",
      "parents": [
        "6769d31ddbab341940af9b42b538fca60797fdf4"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Oct 18 14:02:57 2019 +0100"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Wed Oct 23 11:47:44 2019 +0100"
      },
      "message": "xilinx: Add URAM288 mapping for xcup\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "6769d31ddbab341940af9b42b538fca60797fdf4",
      "tree": "a80cd15e8fdd3d4cf58ea30a7596c5d6a2a8b64b",
      "parents": [
        "f02623abb5d8338f034d7069844418af8912ab0f"
      ],
      "author": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Fri Oct 18 13:24:19 2019 +0100"
      },
      "committer": {
        "name": "David Shah",
        "email": "dave@ds0.me",
        "time": "Wed Oct 23 11:47:37 2019 +0100"
      },
      "message": "xilinx: Add support for UltraScale[+] BRAM mapping\n\nSigned-off-by: David Shah \u003cdave@ds0.me\u003e\n"
    },
    {
      "commit": "f02623abb5d8338f034d7069844418af8912ab0f",
      "tree": "01d8d8d5ad16a0e4f997e7d39b023a32f818be54",
      "parents": [
        "7b350cacd410b16fdac5a6933aea1bb009b83621"
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      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Oct 23 00:04:34 2019 +0200"
      },
      "committer": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Wed Oct 23 00:04:34 2019 +0200"
      },
      "message": "Bugfix in smtio vcd handling of $-identifiers\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n"
    },
    {
      "commit": "7b350cacd410b16fdac5a6933aea1bb009b83621",
      "tree": "934e58717f9ba5463d97d56eaf8c82d875677494",
      "parents": [
        "a3a7bb9bf7160d434db7a4737e68f6b015b221ef"
      ],
      "author": {
        "name": "Marcin Kościelnicki",
        "email": "koriakin@0x04.net",
        "time": "Tue Oct 08 17:00:30 2019 +0000"
      },
      "committer": {
        "name": "Marcin Kościelnicki",
        "email": "koriakin@0x04.net",
        "time": "Tue Oct 22 18:06:57 2019 +0200"
      },
      "message": "xilinx: Support multiplier mapping for all families.\n\nThis supports several older families that are not yet supported for\nactual logic synthesis — the intention is to add them soon.\n"
    },
    {
      "commit": "a3a7bb9bf7160d434db7a4737e68f6b015b221ef",
      "tree": "752e1d94d353e6969cd0c7f324ee3e819e435e2d",
      "parents": [
        "5025aab8c9b47e2a201f7ffd494475882db92398",
        "3b405d985e789ecf0082f724d2d62d3752e4b60c"
      ],
      "author": {
        "name": "Clifford Wolf",
        "email": "clifford@clifford.at",
        "time": "Tue Oct 22 17:36:54 2019 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Oct 22 17:36:54 2019 +0200"
      },
      "message": "Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg\n\nCall memory_dff before DSP mapping to reserve registers (fixes #1447)"
    },
    {
      "commit": "83fbfe0964dc7315ca6d508e6069507250d9f093",
      "tree": "c64a7a245bf239abbbab15fb63fb7225dadad931",
      "parents": [
        "03457ee13e36574add688a9c2c5c0641a4d6df05"
      ],
      "author": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 21 16:25:15 2019 +0200"
      },
      "committer": {
        "name": "Pepijn de Vos",
        "email": "pepijndevos@gmail.com",
        "time": "Mon Oct 21 16:25:15 2019 +0200"
      },
      "message": "Add some tests\n\nCopied from Efinix.\n\n* fsm is broken\n* latch and tribuf are not implemented yet\n* memory maps to dram\n"
    }
  ],
  "next": "03457ee13e36574add688a9c2c5c0641a4d6df05"
}