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foss-fpga-tools/vtr-xml-utils/019930434c4f9e441932691629345b7228656ef8
commit
019930434c4f9e441932691629345b7228656ef8
[log]
author
Karol Gugala <kgugala@antmicro.com>
Fri Nov 08 16:17:09 2019 +0100
committer
GitHub <noreply@github.com>
Fri Nov 08 16:17:09 2019 +0100
tree
a053f588975401240b550eaf28d45046fc3be05d
parent
946909662eec3fd19fb7190b36d02fe9809756ee [diff]
parent
15bf462cd3d041bdf210989960621e1d4da38bb3 [diff]
Merge pull request #1 from antmicro/initial-module-implementation

Initial module implementation
tree: a053f588975401240b550eaf28d45046fc3be05d
  1. tests/
  2. vtr_xml_utils/
  3. .gitignore
  4. .travis.yml
  5. CODE_OF_CONDUCT.md
  6. CONTRIBUTING.md
  7. COPYING
  8. MANIFEST.in
  9. README.md
  10. requirements.txt
  11. setup.cfg
  12. setup.py
  13. tox.ini
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.