Google Git
Sign in
foss-fpga-tools/vtr-xml-utils/0cee4950a67a7ac893c7ae7ab5a58dbce9b2f1ad
commit
0cee4950a67a7ac893c7ae7ab5a58dbce9b2f1ad
[log]
author
Fahrican Koşar <duck2@protonmail.com>
Sat Sep 07 04:09:36 2019 +0300
committer
Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree
951fa6a9ebf91848fd7ce0c8243a576a23878fa5
parent
e86d288f862ee6d0f559423af265ad409d5b8f18 [diff]
more arch schema fixes

Signed-off-by: Fahrican Koşar <duck2@protonmail.com>
1 file changed
tree: 951fa6a9ebf91848fd7ce0c8243a576a23878fa5
  1. .gitignore/
  2. convert_and_merge_composable_tests/
  3. vtr_xml_utils/
  4. attribute-fixes.xsl
  5. CMakeLists.txt
  6. CODE_OF_CONDUCT.md
  7. CONTRIBUTING.md
  8. convert-pb_type-attributes.xsl
  9. convert-port-tag.xsl
  10. convert-prefix-port.xsl
  11. convert_and_merge_composable_fpga_architecture.sh
  12. COPYING
  13. fpga_architecture.xsd
  14. identity.xsl
  15. pack-patterns.xsl
  16. packed_netlist.xsd
  17. README.md
  18. remove-duplicate-models.xsl
  19. routing_resource.xsd
  20. setup.cfg
  21. setup.py
  22. sort-tags.xsl
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.