| commit | d6ba1f17513ea2e83bc47fcec4248f6650f42857 | [log] [tgz] |
|---|---|---|
| author | Tim Ansell <me@mith.ro> | Mon Dec 07 08:57:14 2020 -0800 |
| committer | GitHub <noreply@github.com> | Mon Dec 07 08:57:14 2020 -0800 |
| tree | fe9bfaabe4422e9e2b80ba75f38a49b375a2ee07 | |
| parent | 40487d49b8323e1a0d87788ee8dc7cf31a2f457a [diff] | |
| parent | 0db507daaf6ccc59ab295f30dc320be61353731c [diff] |
Merge pull request #10 from antmicro/update_licensing Updating copyright headers to match current best practices
This repository contains utilities for working with Verilog to Routing XML files.