commit: 1b87855b6d89b41a8e8bf3390331c2e601430272
[log]
author: Jeppe Johansen <jeppe@j-software.dk>
Tue Jul 17 13:06:22 2018 +0200
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: e3a0768c75d6fbdde4a870c103a98dfb4f65ef04
parent: 219c0edf5ff3092bfe54c26afb5bb6a36c12b752 [diff]

Changed strings to space separated list types.

Signed-off-by: Jeppe Johansen <jeppe@j-software.dk>

fpga_architecture.xsd[diff]

1 file changed

tree: e3a0768c75d6fbdde4a870c103a98dfb4f65ef04

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.