commit: 26e4427eeee02103697ffb7a236854681728ce0c
[log]
author: Alessandro Comodi <acomodi@antmicro.com>
Tue Apr 16 15:24:06 2019 +0200
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: 4efd0134cab2f7ed9c111662a5046e92bdfcd608
parent: 9f94cfe44712aac89252f73a106325b152785562 [diff]

utils/vlog: solved issues with combinational/sequential sinks

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

1 file changed

tree: 4efd0134cab2f7ed9c111662a5046e92bdfcd608

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.