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foss-fpga-tools/vtr-xml-utils/3085166bc0ef0037a6b2292dc27a543fae1b053a
commit
3085166bc0ef0037a6b2292dc27a543fae1b053a
[log]
author
Tim 'mithro' Ansell <me@mith.ro>
Wed May 22 16:38:30 2019 -0700
committer
Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree
60789681cab7f32064f6b9502d16de177cddf6d5
parent
70a26801414f0e8a0abd593e4942826842f7b4b4 [diff]
xml: Better whitespace output and other cleanup.

 * Don't touch existing stuff which already has a parent.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
6 files changed
tree: 60789681cab7f32064f6b9502d16de177cddf6d5
  1. .gitignore/
  2. convert_and_merge_composable_tests/
  3. vtr_xml_utils/
  4. attribute-fixes.xsl
  5. CMakeLists.txt
  6. CODE_OF_CONDUCT.md
  7. CONTRIBUTING.md
  8. convert-port-tag.xsl
  9. convert-prefix-port.xsl
  10. convert_and_merge_composable_fpga_architecture.sh
  11. COPYING
  12. fpga_architecture.xsd
  13. identity.xsl
  14. pack-patterns.xsl
  15. packed_netlist.xsd
  16. README.md
  17. remove-duplicate-models.xsl
  18. routing_resource.xsd
  19. setup.cfg
  20. setup.py
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.