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foss-fpga-tools/vtr-xml-utils/51c82735a942672b120dde64b14857de32277caa
commit
51c82735a942672b120dde64b14857de32277caa
[log]
author
Tim 'mithro' Ansell <me@mith.ro>
Sat May 25 15:51:31 2019 -0700
committer
Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree
034edd4ea0d13c4f5914b7d6b641679db4b1b6ba
parent
4ffd8ad7c83ee40aa12443ec3e30afb216b923b7 [diff]
xml: Adding tiles schema.

This change needs validation, I've never done xsd before.

Fixes #774

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
1 file changed
tree: 034edd4ea0d13c4f5914b7d6b641679db4b1b6ba
  1. .gitignore/
  2. convert_and_merge_composable_tests/
  3. vtr_xml_utils/
  4. attribute-fixes.xsl
  5. CMakeLists.txt
  6. CODE_OF_CONDUCT.md
  7. CONTRIBUTING.md
  8. convert-pb_type-attributes.xsl
  9. convert-port-tag.xsl
  10. convert-prefix-port.xsl
  11. convert_and_merge_composable_fpga_architecture.sh
  12. COPYING
  13. fpga_architecture.xsd
  14. identity.xsl
  15. pack-patterns.xsl
  16. packed_netlist.xsd
  17. README.md
  18. remove-duplicate-models.xsl
  19. routing_resource.xsd
  20. setup.cfg
  21. setup.py
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.