commit: fb783cb742386b10e2b7e5fc94d10a0465f029a2
[log]
author: Jeffrey Elms <elmsfu@freshred.net>
Wed Aug 29 11:28:48 2018 -0700
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: c3f560ee07a3bdd74d40aaaac448ce647e80376e
parent: 96e5d36d28c0fcd48ce27ca3be488078863da463 [diff]

make: xmllint passes on testarch and ice40

Signed-off-by: Jeffrey Elms <elmsfu@freshred.net>

fpga_architecture.xsd[diff]

1 file changed

tree: c3f560ee07a3bdd74d40aaaac448ce647e80376e

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.