commit: 66819b8c48d49631499282866977ce9818aa4074
[log]
author: Tim 'mithro' Ansell <me@mith.ro>
Tue May 14 20:26:42 2019 -0700
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: e3190408de3a15465ce2dd1b5a92d086b304d79f
parent: 16278219479343a0b5005d45dd672733ae1d9add [diff]

xml: Make sure existing interconnect is preserved.

(Plus add test.)

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

4 files changed

tree: e3190408de3a15465ce2dd1b5a92d086b304d79f

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.