diff --git a/convert_and_merge_composable_fpga_architecture.xsl b/convert_and_merge_composable_fpga_architecture.xsl
index 7592168..884a52b 100644
--- a/convert_and_merge_composable_fpga_architecture.xsl
+++ b/convert_and_merge_composable_fpga_architecture.xsl
@@ -122,12 +122,14 @@
 	        <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
           <xsl:if test="position() != last()"><xsl:text> </xsl:text></xsl:if>
         </xsl:for-each>
+        <xsl:value-of select="@input" />
       </xsl:attribute>
       <xsl:attribute name="output">
         <xsl:for-each select="port[@type='output']">
 	        <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
           <xsl:if test="position() != last()"><xsl:text> </xsl:text></xsl:if>
         </xsl:for-each>
+        <xsl:value-of select="@output" />
       </xsl:attribute>
       <xsl:if test="*/metadata">
         <metadata>
diff --git a/convert_and_merge_composable_tests/CMakeLists.txt b/convert_and_merge_composable_tests/CMakeLists.txt
index 0f8cf86..0ef0e5b 100644
--- a/convert_and_merge_composable_tests/CMakeLists.txt
+++ b/convert_and_merge_composable_tests/CMakeLists.txt
@@ -8,6 +8,7 @@
 xsl_golden_test(NAME "explicit-port")
 xsl_golden_test(NAME "pack_pattern-merge-type-into-name")
 xsl_golden_test(NAME "pack_pattern-strip-from-pb_type-ports")
+xsl_golden_test(NAME "preserve-interconnect")
 # Test everything used together in one big file
 add_file_target(FILE "full-test-inner.xml" SCANNER_TYPE xml)
 xsl_golden_test(NAME "full-test")
diff --git a/convert_and_merge_composable_tests/preserve-interconnect.golden.xml b/convert_and_merge_composable_tests/preserve-interconnect.golden.xml
new file mode 100644
index 0000000..43c72d0
--- /dev/null
+++ b/convert_and_merge_composable_tests/preserve-interconnect.golden.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<xml>
+  <pb_type name="parent">
+    <input name="ia1"/>
+    <input name="ia2"/>
+    <input name="ia3"/>
+    <output name="o0"/>
+    <output name="o1"/>
+    <pb_type name="childa">
+      <input name="i1"/>
+      <input name="i2"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childb">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childc">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <interconnect>
+      <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
+      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2"/>
+      <direct input="childa.o" name="parent-o0" output="parent.o0"/>
+      <direct input="childa.o" name="childb-i" output="childb.i"/>
+      <mux name="childc-input" input="childa.o childb.o" output="childc.i"/>
+      <mux name="output" input="childa.o childb.o childc.o" output="parent.o1"/>
+    </interconnect>
+  </pb_type>
+</xml>
diff --git a/convert_and_merge_composable_tests/preserve-interconnect.xml b/convert_and_merge_composable_tests/preserve-interconnect.xml
new file mode 100644
index 0000000..bcdffaa
--- /dev/null
+++ b/convert_and_merge_composable_tests/preserve-interconnect.xml
@@ -0,0 +1,32 @@
+<?xml version="1.0"?>
+<!-- Make sure existing interconnect values are preserved. -->
+<xml>
+  <pb_type name="parent">
+    <input name="ia1"/>
+    <input name="ia2"/>
+    <input name="ia3"/>
+    <output name="o0"/>
+    <output name="o1"/>
+    <pb_type name="childa">
+      <input name="i1"/>
+      <input name="i2"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childb">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childc">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <interconnect>
+      <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
+      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2"/>
+      <direct input="childa.o" name="parent-o0" output="parent.o0"/>
+      <direct input="childa.o" name="childb-i" output="childb.i"/>
+      <mux name="childc-input" input="childa.o childb.o" output="childc.i"/>
+      <mux name="output" input="childa.o childb.o childc.o" output="parent.o1"/>
+    </interconnect>
+  </pb_type>
+</xml>