commit: 24403f9f705ba8d41ee925899b5dc305eea943c3
[log]
author: Tim 'mithro' Ansell <me@mith.ro>
Tue May 21 00:32:21 2019 -0700
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: 99e2d4b32aa450ccf8c1c140194ac494eb2b4234
parent: 333775c1a7d4342418ed7a2b6b78e37ec46008f5 [diff]

xml: Adding Cinternal to XML schema.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

2 files changed

tree: 99e2d4b32aa450ccf8c1c140194ac494eb2b4234

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.