tree e9d8406b0f9f17550599a8ea22ea4a51ae122fb0
parent 24403f9f705ba8d41ee925899b5dc305eea943c3
author Tim 'mithro' Ansell <me@mith.ro> 1557859338 -0700
committer Grzegorz Latosinski <glatosinski@antmicro.com> 1573210038 +0100

xml: Improve xslt transform.

Continue to improve the `xmlsort.xsl` script to be a tool which merges a
modified FPGA architecture.

Currently it also converts a more composable format and converts it into
the format that VtR accepts. Eventually the hope is that upstream VtR
will accept this composable format in the future. See;
https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/272

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>