commit: 7e25582940f792eef29222a9e0baa7fd8508da58
[log]
author: Elms <elms@freshred.net>
Mon Mar 11 23:08:21 2019 -0700
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: 36f17891a263059964470588b1c16ec8133d2658
parent: 5cfe5af0930bd656ef94a3bdf8fbae2e16138170 [diff]

Update XSD to support metadata in interconnect

Signed-off-by: Elms <elms@freshred.net>

fpga_architecture.xsd[diff]

1 file changed

tree: 36f17891a263059964470588b1c16ec8133d2658

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.