diff --git a/convert_and_merge_composable_fpga_architecture.xsl b/convert_and_merge_composable_fpga_architecture.xsl
index 884a52b..ad1332f 100644
--- a/convert_and_merge_composable_fpga_architecture.xsl
+++ b/convert_and_merge_composable_fpga_architecture.xsl
@@ -65,11 +65,17 @@
        <pack_pattern name="yyy-xxx"
     -->
   <xsl:template match="pack_pattern/@type"/>
-  <xsl:template match="pack_pattern/@name">
+  <xsl:template match="pack_pattern[@type]/@name">
     <xsl:attribute name="name">
       <xsl:value-of select="../@type"/>-<xsl:value-of select="../@name"/>
     </xsl:attribute>
   </xsl:template>
+  <xsl:template match="pack_pattern[not(@type)]/@name">
+    <xsl:copy />
+  </xsl:template>
+  <xsl:template match="pack_pattern/*">
+    <xsl:copy />
+  </xsl:template>
 
   <!-- Prefix in_port / out_port values with the parent name. -->
   <xsl:template match="@out_port">
@@ -95,14 +101,14 @@
 
   <!--
     Convert
-      <interconnect><direct><pack_pattern><port type='input' ...><port type='output' ...></pack_pattern></direct><YYY../></interconnect>
+      <interconnect><xxx><pack_pattern><port type='input' ...><port type='output' ...></pack_pattern></xxx><YYY../></interconnect>
     to
-      <interconnect><direct><pack_pattern in_port="XXXX" out_port="XXXX" /></direct></interconnect>
+      <interconnect><xxx><pack_pattern in_port="XXXX" out_port="XXXX" /></xxx></interconnect>
     -->
-  <xsl:template match="interconnect/direct/pack_pattern/port[@type='input']">
+  <xsl:template match="pack_pattern/port[@type='input']">
     <xsl:attribute name="in_port"><xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/></xsl:attribute>
   </xsl:template>
-  <xsl:template match="interconnect/direct/pack_pattern/port[@type='output']">
+  <xsl:template match="pack_pattern/port[@type='output']">
     <xsl:attribute name="out_port"><xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/></xsl:attribute>
   </xsl:template>
 
@@ -112,25 +118,22 @@
     to
       <interconnect><mux input='in1 in2' name='xxx-xxx' output='...'><YYY../></mux></interconnect>
     -->
+  <xsl:template match="interconnect/mux/port"></xsl:template>
   <xsl:template match="interconnect/mux">
     <xsl:copy>
-      <xsl:attribute name="name">
-        <xsl:value-of select="@name" />
-      </xsl:attribute>
       <xsl:attribute name="input">
         <xsl:for-each select="port[@type='input']">
-	        <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
+          <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
           <xsl:if test="position() != last()"><xsl:text> </xsl:text></xsl:if>
         </xsl:for-each>
-        <xsl:value-of select="@input" />
       </xsl:attribute>
       <xsl:attribute name="output">
         <xsl:for-each select="port[@type='output']">
-	        <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
-          <xsl:if test="position() != last()"><xsl:text> </xsl:text></xsl:if>
+          <xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/>
         </xsl:for-each>
-        <xsl:value-of select="@output" />
       </xsl:attribute>
+      <xsl:for-each select="@*"><xsl:copy /></xsl:for-each>
+      <xsl:apply-templates/>
       <xsl:if test="*/metadata">
         <metadata>
           <!-- The fasm_mux metadata attribute needs special handling. -->
@@ -138,8 +141,8 @@
             <meta name="fasm_mux">
               <xsl:for-each select="port[@type='input']"><xsl:text>
                 </xsl:text><xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/><xsl:text> : </xsl:text><xsl:value-of select="metadata/meta[@name='fasm_mux']" />
-	            </xsl:for-each><xsl:text>
-          </xsl:text>
+              </xsl:for-each><xsl:text>
+            </xsl:text>
             </meta>
           </xsl:if>
           <xsl:for-each select="metadata">
@@ -149,6 +152,7 @@
       </xsl:if>
     </xsl:copy>
   </xsl:template>
+  <xsl:template match="interconnect/mux/metadata"></xsl:template>
 
   <!--
     Convert
diff --git a/convert_and_merge_composable_tests/CMakeLists.txt b/convert_and_merge_composable_tests/CMakeLists.txt
index 0ef0e5b..7a6f5de 100644
--- a/convert_and_merge_composable_tests/CMakeLists.txt
+++ b/convert_and_merge_composable_tests/CMakeLists.txt
@@ -4,6 +4,7 @@
 xsl_golden_test(NAME "composable-interconnect-fasm-mux")
 xsl_golden_test(NAME "composable-interconnect-fasm-mux-levels")
 xsl_golden_test(NAME "composable-interconnect-implicit-parent")
+xsl_golden_test(NAME "composable-interconnect-pack_patterns")
 xsl_golden_test(NAME "composable-loc-implicit-parent")
 xsl_golden_test(NAME "explicit-port")
 xsl_golden_test(NAME "pack_pattern-merge-type-into-name")
diff --git a/convert_and_merge_composable_tests/composable-interconnect-fasm-mux-levels.golden.xml b/convert_and_merge_composable_tests/composable-interconnect-fasm-mux-levels.golden.xml
index ca6f259..c103723 100644
--- a/convert_and_merge_composable_tests/composable-interconnect-fasm-mux-levels.golden.xml
+++ b/convert_and_merge_composable_tests/composable-interconnect-fasm-mux-levels.golden.xml
@@ -21,14 +21,14 @@
       <output name="o"/>
     </pb_type>
     <interconnect>
-      <mux name="outmux" input="blocka.a blockb.b blockc[0].c blockc[1].c" output="blocko.i">
+      <mux input="blocka.a blockb.b blockc[0].c blockc[1].c" output="blocko.i" name="outmux">
         <metadata>
           <meta name="fasm_mux">
                 blocka.a : a1
                 blockb.b : b1.l1
                 blockc[0].c : c0.l1
                 blockc[1].c : c1
-          </meta>
+            </meta>
           <meta name="fasm_name">fasm_name</meta>
         </metadata>
       </mux>
diff --git a/convert_and_merge_composable_tests/composable-interconnect-fasm-mux.golden.xml b/convert_and_merge_composable_tests/composable-interconnect-fasm-mux.golden.xml
index b0d5c1a..21c5cb3 100644
--- a/convert_and_merge_composable_tests/composable-interconnect-fasm-mux.golden.xml
+++ b/convert_and_merge_composable_tests/composable-interconnect-fasm-mux.golden.xml
@@ -10,12 +10,12 @@
     </pb_type>
     <interconnect>
       <direct name="parent-o" output="parent.o" input="child.o"/>
-      <mux name="mux1" input="parent.i0 parent.i1" output="child.i">
+      <mux input="parent.i0 parent.i1" output="child.i" name="mux1">
         <metadata>
           <meta name="fasm_mux">
                 parent.i0 : a1
                 parent.i1 : b1
-          </meta>
+            </meta>
           <meta name="fasm_name">fasm_name</meta>
         </metadata>
       </mux>
diff --git a/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.golden.xml b/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.golden.xml
index 43c72d0..12abd36 100644
--- a/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.golden.xml
+++ b/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.golden.xml
@@ -20,12 +20,17 @@
       <output name="o"/>
     </pb_type>
     <interconnect>
-      <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
-      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2"/>
+      <direct input="parent.ia1" name="childa-i1" output="childa.i1">
+        <pack_pattern name="A1" in_port="parent.ia1" out_port="childa.i1"/>
+      </direct>
+      <mux input="parent.ia2 parent.ia3" output="childa.i2" name="childa-input-i2">
+        <pack_pattern name="A2" in_port="parent.ia2" out_port="childa.i2"/>
+        <pack_pattern name="A3" in_port="parent.ia3" out_port="childa.i2"/>
+      </mux>
       <direct input="childa.o" name="parent-o0" output="parent.o0"/>
       <direct input="childa.o" name="childb-i" output="childb.i"/>
-      <mux name="childc-input" input="childa.o childb.o" output="childc.i"/>
-      <mux name="output" input="childa.o childb.o childc.o" output="parent.o1"/>
+      <mux input="childa.o childb.o" output="childc.i" name="childc-input"/>
+      <mux input="childa.o childb.o childc.o" output="parent.o1" name="output"/>
     </interconnect>
   </pb_type>
 </xml>
diff --git a/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.xml b/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.xml
index 5d8a28c..089159f 100644
--- a/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.xml
+++ b/convert_and_merge_composable_tests/composable-interconnect-implicit-parent.xml
@@ -59,12 +59,24 @@
     <direct>
      <port type="input"                name="ia1" />
      <port type="output" from="childa" name="i1"  />
+     <pack_pattern name="A1">
+      <port type="input"                name="ia1" />
+      <port type="output" from="childa" name="i1"  />
+     </pack_pattern>
     </direct>
     <!-- Mux parent -> child -->
     <mux name="childa-input-i2">
      <port type="input"                name="ia2" />
      <port type="input"                name="ia3" />
      <port type="output" from="childa" name="i2"  />
+     <pack_pattern name="A2">
+      <port type="input"                name="ia2" />
+      <port type="output" from="childa" name="i2"  />
+     </pack_pattern>
+     <pack_pattern name="A3">
+      <port type="input"                name="ia3" />
+      <port type="output" from="childa" name="i2"  />
+     </pack_pattern>
     </mux>
     <!-- Direct parent -> child -->
     <direct>
diff --git a/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.golden.xml b/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.golden.xml
new file mode 100644
index 0000000..ae06303
--- /dev/null
+++ b/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.golden.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<xml>
+  <pb_type name="parent">
+    <input name="ia1"/>
+    <input name="ia2"/>
+    <input name="ia3"/>
+    <output name="o0"/>
+    <output name="o1"/>
+    <pb_type name="childa">
+      <input name="i1"/>
+      <input name="i2"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childb">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <pb_type name="childc">
+      <input name="i"/>
+      <output name="o"/>
+    </pb_type>
+    <interconnect>
+      <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
+      <mux input="parent.ia2 parent.ia3" output="childa.i2" name="childa-input-i2"/>
+      <direct input="childa.o" name="parent-o0" output="parent.o0"/>
+      <direct input="childa.o" name="childb-i" output="childb.i"/>
+      <mux input="childa.o childb.o" output="childc.i" name="childc-input"/>
+      <mux input="childa.o childb.o childc.o" output="parent.o1" name="output"/>
+    </interconnect>
+  </pb_type>
+</xml>
diff --git a/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.xml b/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.xml
new file mode 100644
index 0000000..5d8a28c
--- /dev/null
+++ b/convert_and_merge_composable_tests/composable-interconnect-pack_patterns.xml
@@ -0,0 +1,95 @@
+<?xml version="1.0"?>
+<!--
+  Convert "implicit" parent specification for interconnect tags.
+
+  Convert
+    <interconnect><direct><port type='input' ...><port type='output' ...></direct><YYY../></interconnect>
+  to
+    <interconnect><direct input='...' name='xxx-xxx' output='...'><YYY../></direct></interconnect>
+
+  Convert
+    <interconnect><mux><port type='input' ...><port type='input' ...><port type='output' ...></mux><YYY../></interconnect>
+  to
+    <interconnect><mux input='in1 in2' name='xxx-xxx' output='...'><YYY../></mux></interconnect>
+
+This example below is connected as follows;
+     ┌───────────────────────────────────────────────────────────────────┐
+     │                                                                   │
+     │       ┌────────────┐                                              │
+  ia1│──────>│i1          │                                              │
+     │       │            │                                              │
+     │       │   childa  o│─┬───────────────────────────────────────────>│o0
+  ia2│──>│╲  │            │ │                                            │
+     │   │├─>│i2          │ │                                            │
+  ia3│──>│╱  └────────────┘ │  ┌──────────┐                              │
+     │                      ├─>│i childb o│─┬──>│╲                       │
+     │                      │  └──────────┘ │   ││   ┌──────────┐        │
+     │                      │               │   │├──>│i childc o│──>│╲   │
+     │                      ├──────────────────>││   └──────────┘   ││   │
+     │                      │               │   │╱                  ││   │
+     │                      │               │             ╭────────>│├──>│o1
+     │                      │               ╰─────────────╯         ││   │
+     │                      │                                       ││   │
+     │                      ╰──────────────────────────────────────>│/   │
+     │                                                                   │
+     └───────────────────────────────────────────────────────────────────┘
+  -->
+<xml>
+ <pb_type name="parent">
+  <input name="ia1"/>
+  <input name="ia2"/>
+  <input name="ia3"/>
+  <output name="o0"/>
+  <output name="o1"/>
+  <pb_type name="childa">
+    <input name="i1"/>
+    <input name="i2"/>
+    <output name="o"/>
+  </pb_type>
+  <pb_type name="childb">
+    <input name="i"/>
+    <output name="o"/>
+    </pb_type>
+    <pb_type name="childc">
+    <input name="i"/>
+    <output name="o"/>
+  </pb_type>
+  <interconnect>
+    <!-- Direct parent -> child -->
+    <direct>
+     <port type="input"                name="ia1" />
+     <port type="output" from="childa" name="i1"  />
+    </direct>
+    <!-- Mux parent -> child -->
+    <mux name="childa-input-i2">
+     <port type="input"                name="ia2" />
+     <port type="input"                name="ia3" />
+     <port type="output" from="childa" name="i2"  />
+    </mux>
+    <!-- Direct parent -> child -->
+    <direct>
+     <port type="input"  from="childa" name="o"   />
+     <port type="output"               name="o0"  />
+    </direct>
+    <!-- Direct child -> child -->
+    <direct>
+     <port type="input"  from="childa" name="o"   />
+     <port type="output" from="childb" name="i"   />
+    </direct>
+    <!-- Mux child -> child -->
+    <mux name="childc-input">
+     <port type="input"  from="childa" name="o"   />
+     <port type="input"  from="childb" name="o"   />
+     <port type="output" from="childc" name="i"   />
+    </mux>
+    <!-- Mux child -> parent -->
+    <mux name="output">
+     <port type="input"  from="childa" name="o"   />
+     <port type="input"  from="childb" name="o"   />
+     <port type="input"  from="childc" name="o"   />
+     <port type="output"               name="o1"  />
+    </mux>
+  </interconnect>
+ </pb_type>
+</xml>
+
diff --git a/convert_and_merge_composable_tests/preserve-interconnect.golden.xml b/convert_and_merge_composable_tests/preserve-interconnect.golden.xml
index 43c72d0..8023868 100644
--- a/convert_and_merge_composable_tests/preserve-interconnect.golden.xml
+++ b/convert_and_merge_composable_tests/preserve-interconnect.golden.xml
@@ -21,11 +21,16 @@
     </pb_type>
     <interconnect>
       <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
-      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2"/>
-      <direct input="childa.o" name="parent-o0" output="parent.o0"/>
+      <mux input="parent.ia2 parent.ia3" output="childa.i2" name="childa-input-i2">
+        <pack_pattern in_port="parent.parent.ia2" name="MUX1" output="childa.i2"/>
+        <pack_pattern in_port="parent.parent.ia3" name="MUX2" output="childa.i2"/>
+      </mux>
+      <direct input="childa.o" name="parent-o0" output="parent.o0">
+        <pack_pattern in_port="parent.childa.o" name="CARRY" output="parent.o0"/>
+      </direct>
       <direct input="childa.o" name="childb-i" output="childb.i"/>
-      <mux name="childc-input" input="childa.o childb.o" output="childc.i"/>
-      <mux name="output" input="childa.o childb.o childc.o" output="parent.o1"/>
+      <mux input="childa.o childb.o" output="childc.i" name="childc-input"/>
+      <mux input="childa.o childb.o childc.o" output="parent.o1" name="output"/>
     </interconnect>
   </pb_type>
 </xml>
diff --git a/convert_and_merge_composable_tests/preserve-interconnect.xml b/convert_and_merge_composable_tests/preserve-interconnect.xml
index bcdffaa..1053784 100644
--- a/convert_and_merge_composable_tests/preserve-interconnect.xml
+++ b/convert_and_merge_composable_tests/preserve-interconnect.xml
@@ -22,8 +22,13 @@
     </pb_type>
     <interconnect>
       <direct input="parent.ia1" name="childa-i1" output="childa.i1"/>
-      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2"/>
-      <direct input="childa.o" name="parent-o0" output="parent.o0"/>
+      <mux name="childa-input-i2" input="parent.ia2 parent.ia3" output="childa.i2">
+	<pack_pattern name="MUX1" in_port="parent.ia2" output="childa.i2" />
+	<pack_pattern name="MUX2" in_port="parent.ia3" output="childa.i2" />
+      </mux>
+      <direct input="childa.o" name="parent-o0" output="parent.o0">
+	<pack_pattern name="CARRY" in_port="childa.o" output="parent.o0" />
+      </direct>
       <direct input="childa.o" name="childb-i" output="childb.i"/>
       <mux name="childc-input" input="childa.o childb.o" output="childc.i"/>
       <mux name="output" input="childa.o childb.o childc.o" output="parent.o1"/>