)]}'
{
  "commit": "90331f020e37fecc84f794c08eb85527db483c74",
  "tree": "a327513d2154d81e17c6ad9c8f675fd62291b952",
  "parents": [
    "e369525077685917e5a2d3a9f18862d5a83fac37"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Jul 04 10:55:27 2018 -0700"
  },
  "committer": {
    "name": "Grzegorz Latosinski",
    "email": "glatosinski@antmicro.com",
    "time": "Fri Nov 08 11:47:18 2019 +0100"
  },
  "message": "xml: Slight change in VPR XML format.\n\nSupport a format for pb_type which doesn\u0027t require repeating the name\nmany times. Use the xmlsort style sheet to generate the old XML version.\n\nThe changes are;\n * Remove the requirement to give an interconnect a name.\n * Moving from attributes for input/output to \"port\" tags.\n * Decompose the old \u0027PB_TYPE.PORT[BIT]\u0027 into attributes on \"port\" tag.\n * \"Port\" tags have a \u0027from\u0027 attribute. If left blank it defaults to the\n   current pb_type.\n\nBefore;\n```xml\n\u003cdirect input\u003d\"XXXX.CLOCK_ENABLE\" output\u003d\"in_cen.EN\" name\u003d\"XXXX\"\u003e\n```\n\nAfter;\n```xml\n\u003cdirect\u003e\n  \u003cport name\u003d\"CLOCK_ENABLE\" type\u003d\"input\"/\u003e\n  \u003cport name\u003d\"EN\" type\u003d\"output\" from\u003d\"in_cen\"/\u003e\n\u003c/direct\u003e\n```\n\nDisadvantages:\n * This is more verbose.\n\nAdvantages:\n * The \u0027default to current pb_type\u0027 means that you can do;\n```xml\n\u003cpb_type name\u003d\"tristate\" num_pb\u003d\"1\"\u003e\n  \u003cxi:include href\u003d\"../tri/io_tri.pb_type.xml\" xpointer\u003d\"xpointer(pb_type/child::node())\"/\u003e\n\u003c/pb_type\u003e\n```\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b61d4737294a2e095c7d1d22d36fa8d8f44fb118",
      "old_mode": 33188,
      "old_path": "xmlsort.xsl",
      "new_id": "49c174997f172e222f644f35a6e54c383ff6cfa9",
      "new_mode": 33188,
      "new_path": "xmlsort.xsl"
    }
  ]
}