commit: 90672c152e4ea228d3f13d096c243d76102a007f
[log]
author: Tim 'mithro' Ansell <me@mith.ro>
Tue May 21 22:47:56 2019 -0700
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree: eaee9e330c615c4404606a76e55a9540902dc722
parent: c318a8ba186e350ed17fc7d60321a9b4e457afbc [diff]

xml: Use multiple passes in convert and merge script.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

attribute-fixes.xsl[Added - diff]
convert-port-tag.xsl[Renamed from convert_and_merge_composable_fpga_architecture.xsl - diff]
convert-prefix-port.xsl[Added - diff]
convert_and_merge_composable_fpga_architecture.sh[Added - diff]
convert_and_merge_composable_tests/CMakeLists.txt[diff]
convert_and_merge_composable_tests/attribute-cleanup.xml[diff]
convert_and_merge_composable_tests/composable-interconnect-fasm-mux-levels.golden.xml[diff]
convert_and_merge_composable_tests/composable-interconnect-fasm-mux.golden.xml[diff]
convert_and_merge_composable_tests/composable-interconnect-implicit-parent.golden.xml[diff]
convert_and_merge_composable_tests/composable-interconnect-pack_patterns.golden.xml[diff]
convert_and_merge_composable_tests/full-test-inner.xml[diff]
convert_and_merge_composable_tests/full-test.golden.xml[diff]
convert_and_merge_composable_tests/pack_pattern-copy-direct-ports.golden.xml[Added - diff]
convert_and_merge_composable_tests/preserve-interconnect.golden.xml[diff]
identity.xsl[Added - diff]
pack-patterns.xsl[Added - diff]
remove-duplicate-models.xsl[Added - diff]

17 files changed

tree: eaee9e330c615c4404606a76e55a9540902dc722

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.