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foss-fpga-tools/vtr-xml-utils/c7e001fa600d7269ffb2aeef18d654f196cf108e
commit
c7e001fa600d7269ffb2aeef18d654f196cf108e
[log]
author
Alessandro Comodi <acomodi@antmicro.com>
Tue Sep 24 13:21:37 2019 +0200
committer
Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 11:47:18 2019 +0100
tree
2b4139fa4b5359b3b0386e6b97e0bca3629e7658
parent
0faa6ed7c8650a69ca9cfeb9f4ffe4b3270a0696 [diff]
updated fpga_architecture.xsd definitions for xml_lint target

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
1 file changed
tree: 2b4139fa4b5359b3b0386e6b97e0bca3629e7658
  1. .gitignore/
  2. convert_and_merge_composable_tests/
  3. vtr_xml_utils/
  4. attribute-fixes.xsl
  5. CMakeLists.txt
  6. CODE_OF_CONDUCT.md
  7. CONTRIBUTING.md
  8. convert-pb_type-attributes.xsl
  9. convert-port-tag.xsl
  10. convert-prefix-port.xsl
  11. convert_and_merge_composable_fpga_architecture.sh
  12. COPYING
  13. fpga_architecture.xsd
  14. identity.xsl
  15. pack-patterns.xsl
  16. packed_netlist.xsd
  17. README.md
  18. remove-duplicate-models.xsl
  19. routing_resource.xsd
  20. setup.cfg
  21. setup.py
  22. sort-tags.xsl
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.