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foss-fpga-tools/vtr-xml-utils/ba8ef7e5851209a90c93c4cbf6eaf8653f5b762c
commit
ba8ef7e5851209a90c93c4cbf6eaf8653f5b762c
[log]
author
Tim 'mithro' Ansell <me@mith.ro>
Tue May 14 21:19:54 2019 -0700
committer
Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 16:07:06 2019 +0100
tree
b7a77d535ae7c0f881c701ad64f51411c67fc028
parent
aff2053cf74e2a061fc8bc59143e007d8f73ab2e [diff]
xml: Preserve existing interconnect info.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
9 files changed
tree: b7a77d535ae7c0f881c701ad64f51411c67fc028
  1. .gitignore/
  2. vtr_xml_utils/
  3. attribute-cleanup.golden.xml
  4. attribute-cleanup.xml
  5. CMakeLists.txt
  6. CODE_OF_CONDUCT.md
  7. composable-interconnect-fasm-mux-levels.golden.xml
  8. composable-interconnect-fasm-mux-levels.xml
  9. composable-interconnect-fasm-mux.golden.xml
  10. composable-interconnect-fasm-mux.xml
  11. composable-interconnect-implicit-parent.golden.xml
  12. composable-interconnect-implicit-parent.xml
  13. composable-interconnect-pack_patterns.golden.xml
  14. composable-interconnect-pack_patterns.xml
  15. composable-loc-implicit-parent.golden.xml
  16. composable-loc-implicit-parent.xml
  17. CONTRIBUTING.md
  18. COPYING
  19. explicit-port.golden.xml
  20. explicit-port.xml
  21. full-test-inner.xml
  22. full-test.golden.xml
  23. full-test.xml
  24. MANIFEST.in
  25. pack_pattern-merge-type-into-name.golden.xml
  26. pack_pattern-merge-type-into-name.xml
  27. pack_pattern-strip-from-pb_type-ports.golden.xml
  28. pack_pattern-strip-from-pb_type-ports.xml
  29. preserve-interconnect.golden.xml
  30. preserve-interconnect.xml
  31. README.md
  32. setup.cfg
  33. setup.py
  34. tox.ini
  35. xml-explicit-port.xml
  36. xsl_tests.cmake
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.