commit: c15b346189a0bbea8cb972f40d8e23510f28aeb9
[log]
author: Grzegorz Latosinski <glatosinski@antmicro.com>
Thu Nov 07 10:43:59 2019 +0100
committer: Grzegorz Latosinski <glatosinski@antmicro.com>
Fri Nov 08 16:07:06 2019 +0100
tree: c3378e836efb253f487aa103bc1fb93ec2c066fb
parent: 9c2c302848bb0f97a9ad3781e8755208e0721845 [diff]

Added .travis.yml script to the project

Signed-off-by: Grzegorz Latosinski <glatosinski@antmicro.com>

1 file changed

tree: c3378e836efb253f487aa103bc1fb93ec2c066fb

README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.