diff --git a/convert_and_merge_composable_fpga_architecture.xsl b/convert_and_merge_composable_fpga_architecture.xsl
index ad1332f..a8879db 100644
--- a/convert_and_merge_composable_fpga_architecture.xsl
+++ b/convert_and_merge_composable_fpga_architecture.xsl
@@ -99,6 +99,15 @@
     <xsl:attribute name="output"><xsl:call-template name="from-pb_type"/>.<xsl:call-template name="port-value"/></xsl:attribute>
   </xsl:template>
 
+  <xsl:template match="direct/pack_pattern">
+    <xsl:copy>
+      <xsl:attribute name="in_port"><xsl:value-of select="../@input" /></xsl:attribute>
+      <xsl:attribute name="out_port"><xsl:value-of select="../@output" /></xsl:attribute>
+      <xsl:apply-templates select="@*"></xsl:apply-templates>
+    </xsl:copy>
+    <xsl:apply-templates/>
+  </xsl:template>
+
   <!--
     Convert
       <interconnect><xxx><pack_pattern><port type='input' ...><port type='output' ...></pack_pattern></xxx><YYY../></interconnect>
diff --git a/convert_and_merge_composable_tests/pack_pattern-copy-direct-ports.xml b/convert_and_merge_composable_tests/pack_pattern-copy-direct-ports.xml
new file mode 100644
index 0000000..0a23c15
--- /dev/null
+++ b/convert_and_merge_composable_tests/pack_pattern-copy-direct-ports.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!--
+  Convert
+     <direct XXXX><pack_pattern name="xxx"/>
+  to
+     <direct XXXX><pack_pattern name="xxx" XXXX/>
+  -->
+<xml>
+	<interconnect>
+  <direct input="SB_FF.D" name="VPR_FF-D" output="VPR_FF.D">
+    <pack_pattern name="A"/>
+  </direct>
+  <direct>
+   <port type="input" from="LUTFF" name="FCIN"/><port type="output" from="SB_CARRY" name="CI"/>
+   <pack_pattern name="CARRYCHAIN"/>
+  </direct>
+ </interconnect>
+</xml>