)]}'
{
  "commit": "c59810ff8fcc3388a05c9d08dc4af1cf24f135b8",
  "tree": "1a1b7f5625b8f6caa3f7405bcc0342922f8f2b72",
  "parents": [
    "1b87855b6d89b41a8e8bf3390331c2e601430272"
  ],
  "author": {
    "name": "Jeppe Johansen",
    "email": "jeppe@j-software.dk",
    "time": "Tue Jul 17 14:13:16 2018 +0200"
  },
  "committer": {
    "name": "Grzegorz Latosinski",
    "email": "glatosinski@antmicro.com",
    "time": "Fri Nov 08 11:47:18 2019 +0100"
  },
  "message": "Add missing power and clocks elements.\nAdded sb_loc elements.\nChanged pb_type io equivalent to match definitions uses in VPR archdefs.\nMade fs in switch_block optional, as it can be for custom switch_blocks.\nAdded device_layout as an alias for fixed_layout.\n\nSigned-off-by: Jeppe Johansen \u003cjeppe@j-software.dk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4fc6d5078fd4cb4dc1f884729221e055f95b1f2e",
      "old_mode": 33188,
      "old_path": "fpga_architecture.xsd",
      "new_id": "6d93afd695a6a5df6472a5d1715e950b8ce9368d",
      "new_mode": 33188,
      "new_path": "fpga_architecture.xsd"
    }
  ]
}