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{
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  "tree": "29d73751eeaf9204e39dd77a9003e4c14dcdd86e",
  "parents": [
    "90d27acb41fce4dbca162bf4345fa2ba7c3dbf1e"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Tue May 14 11:42:18 2019 -0700"
  },
  "committer": {
    "name": "Grzegorz Latosinski",
    "email": "glatosinski@antmicro.com",
    "time": "Fri Nov 08 16:07:06 2019 +0100"
  },
  "message": "xml: Improve xslt transform.\n\nContinue to improve the `xmlsort.xsl` script to be a tool which merges a\nmodified FPGA architecture.\n\nCurrently it also converts a more composable format and converts it into\nthe format that VtR accepts. Eventually the hope is that upstream VtR\nwill accept this composable format in the future. See;\nhttps://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/272\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n",
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