diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 718241c..b2d146a 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,7 +1,6 @@
 # counter, counter2, pll - test buffer and clock divider propagation
 # set_false_path - test the set_false_path command
 # set_max_delay - test the set_max_delay command
-
 TESTS = counter \
 	counter2 \
 	pll \
@@ -10,42 +9,13 @@
 	pll_approx_equal \
 	set_false_path \
 	set_max_delay
+include $(shell pwd)/../../Makefile_test.common
 
-.PHONY: $(TESTS)
-
-counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
-counter2_verify = $(call compare,counter2,sdc) && $(call compare,counter2,txt)
-pll_verify = $(call compare,pll,sdc)
-pll_div_verify = $(call compare,pll_div,sdc)
-pll_fbout_phase_verify = $(call compare,pll_fbout_phase,sdc)
-pll_approx_equal_verify = $(call compare,pll_approx_equal,sdc)
-set_false_path_verify = $(call compare,set_false_path,sdc)
-set_max_delay_verify = $(call compare,set_max_delay,sdc)
-
-all: $(TESTS)
-compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
-
-define test_tpl =
-$(1): $(1)/$(1).sdc
-	$$($(1)_verify)
-	RETVAL=$$$$? ; \
-	if [ $$$$RETVAL -eq 0 ]; then \
-		echo "$(1) PASS"; \
-		true; \
-	else \
-		echo "$(1) FAIL"; \
-		false; \
-	fi
-
-$(1)/$(1).sdc: $(1)/$(1).v
-	cd $(1); \
-	INPUT_SDC_FILE=$(1).input.sdc \
-	OUTPUT_SDC_FILE=$(1).sdc \
-	yosys -p "tcl $(1).tcl" -l yosys.log
-
-endef
-
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
-
-clean:
-	rm -rf $(foreach test,$(TESTS),$(test)/$(test).sdc $(test)/$(test).txt $(test)/yosys.log)
+counter_verify = $(call diff_test,counter,sdc) && $(call diff_test,counter,txt)
+counter2_verify = $(call diff_test,counter2,sdc) && $(call diff_test,counter2,txt)
+pll_verify = $(call diff_test,pll,sdc)
+pll_div_verify = $(call diff_test,pll_div,sdc)
+pll_fbout_phase_verify = $(call diff_test,pll_fbout_phase,sdc)
+pll_approx_equal_verify = $(call diff_test,pll_approx_equal,sdc)
+set_false_path_verify = $(call diff_test,set_false_path,sdc)
+set_max_delay_verify = $(call diff_test,set_max_delay,sdc)
diff --git a/sdc-plugin/tests/counter/counter.tcl b/sdc-plugin/tests/counter/counter.tcl
index a27caf9..4fcf9be 100644
--- a/sdc-plugin/tests/counter/counter.tcl
+++ b/sdc-plugin/tests/counter/counter.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog counter.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -11,16 +11,16 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design's timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write the clocks to file
-set fh [open counter.txt w]
+set fh [open $::env(DESIGN_TOP).txt w]
 set clocks [get_clocks]
 puts $fh $clocks
 close $fh
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/counter2/counter2.tcl b/sdc-plugin/tests/counter2/counter2.tcl
index 80bce1b..4fcf9be 100644
--- a/sdc-plugin/tests/counter2/counter2.tcl
+++ b/sdc-plugin/tests/counter2/counter2.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog counter2.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -11,16 +11,16 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design's timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write the clocks to file
-set fh [open counter2.txt w]
+set fh [open $::env(DESIGN_TOP).txt w]
 set clocks [get_clocks]
 puts $fh $clocks
 close $fh
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl
index 61e67f6..5a2e3c4 100644
--- a/sdc-plugin/tests/pll/pll.tcl
+++ b/sdc-plugin/tests/pll/pll.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog pll.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -12,10 +12,10 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
index 13c8890..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog pll_approx_equal.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -12,10 +12,10 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl
index f8f0a9f..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_div/pll_div.tcl
+++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog pll_div.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -12,10 +12,10 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
index 6b6db73..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
@@ -3,7 +3,7 @@
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog pll_fbout_phase.v
+read_verilog $::env(DESIGN_TOP).v
 read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
@@ -12,10 +12,10 @@
 synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
 
 # Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
 
 # Propagate the clocks
 propagate_clocks
 
 # Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl
index 39a51c0..a4e01f4 100644
--- a/sdc-plugin/tests/set_false_path/set_false_path.tcl
+++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -3,7 +3,7 @@
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog set_false_path.v
+read_verilog $::env(DESIGN_TOP).v
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
@@ -16,4 +16,4 @@
 # -from clk to bottom_inst/I
 set_false_path -from clk -to bottom_inst.I
 
-write_sdc set_false_path.sdc
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
index 8cfde6a..f2a5b4f 100644
--- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -3,7 +3,7 @@
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
 
-read_verilog set_max_delay.v
+read_verilog $::env(DESIGN_TOP).v
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
@@ -16,4 +16,4 @@
 # -from clk to bottom_inst/I
 set_max_delay 3 -from clk -to bottom_inst.I
 
-write_sdc set_max_delay.sdc
+write_sdc $::env(DESIGN_TOP).sdc