)]}'
{
  "commit": "0251f7518b2b82547c8ff6ff7702d9593c6049e3",
  "tree": "a819f47d3ee8bab3f120ee96b95ca25fc88ca5a3",
  "parents": [
    "544588778e7b51d38ef46761a62d9efa71ed0ea7"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 15 12:56:06 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 15 16:46:02 2023 +0100"
  },
  "message": "systemverilog-plugin: prefer full name in function calls\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d39e88f9389a82affe40cdb7e0eda8eb88d1a6ce",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "f0dbade5aab96a7ee1da86228fb8ca546d1005b1",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}