)]}'
{
  "commit": "08430ec4f53d1cf9d6a2091211d6c5ce501d5486",
  "tree": "7c427150de5d1f9bfed5cf69af97605909cfe217",
  "parents": [
    "a5a59ed95f5473d049d232b8ee93186b4ae8c8c8",
    "681aa553c80b3a0daa00c49a421f8316ac2c3d56"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Feb 08 16:41:08 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Feb 08 16:41:08 2023 +0100"
  },
  "message": "Merge pull request #451 from antmicro/kr/casez\n\nsystemverilog-plugin: add support for case type",
  "tree_diff": []
}