Re added regular D flip-flops and latches.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index feeb46b..ae54ec3 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -124,6 +124,33 @@
endmodule
+(* abc9_flop, lib_whitebox *)
+module dff(
+ output reg Q,
+ input wire D,
+ (* clkbuf_sink *)
+ input wire C
+);
+ initial Q <= 1'b0;
+
+ always @(posedge C)
+ Q <= D;
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffn(
+ output reg Q,
+ input wire D,
+ (* clkbuf_sink *)
+ input wire C
+);
+ initial Q <= 1'b0;
+
+ always @(negedge C)
+ Q <= D;
+
+endmodule
(* abc9_flop, lib_whitebox *)
module dffsre(
