systemverilog: casex: convert Sx to Sz to match yosys frontend
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 0a6f6c9..3eb0e30 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -3450,6 +3450,15 @@
visit_one_to_one({vpiCondition}, obj_h, [&](AST::AstNode *node) { current_node->children.push_back(node); });
visit_one_to_many({vpiCaseItem}, obj_h, [&](AST::AstNode *node) {
node->type = cond_type;
+ // TODO(krak): We are changing here Sx to Sz to match
+ // yosys read_verilog -sv output
+ if (cond_type == AST::AST_CONDX) {
+ for (unsigned i = 0; i < node->bits.size(); i++) {
+ if (node->bits[i] == RTLIL::State::Sx) {
+ node->bits[i] = RTLIL::State::Sz;
+ }
+ }
+ }
current_node->children.push_back(node);
});
}
