)]}'
{
  "commit": "0af8e42609be2602ab0d8083853b44b7bcd79ced",
  "tree": "62b01df44cdff0c46fac12865d512dcd5b241b3b",
  "parents": [
    "79d291d824a84bafe73818debaf5ba51e679edec"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 07 15:09:45 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Feb 07 15:09:45 2023 +0100"
  },
  "message": "systemverilog: casex: convert Sx to Sz to match yosys frontend\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0a6f6c9d24ddc26b1be37b2ed4dfc5b888498d14",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "3eb0e30d9339c2ba458d77a498851d71aebb0f1c",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}