Merge pull request #44 from antmicro/plugin_tests_makefile_cleanup
Create common test Makefile template
diff --git a/Makefile_test.common b/Makefile_test.common
new file mode 100644
index 0000000..fe8ffce
--- /dev/null
+++ b/Makefile_test.common
@@ -0,0 +1,45 @@
+# Each plugin shall have a directory named 'test' that contains test cases
+# directories and a Makefile which includes this Makefile template.
+# The test Makefile specifies which tests to execute and how to verify them.
+# The test to execute should be explicitly specified in the TESTS variable.
+# Each test needs a verification step define in the name_of_test_verify variable.
+# A simple diff verification template have been defined in the template Makefile
+# diff_test performs a simple diff and takes name of file and its extension
+# Example of a test Makefile is given below:
+#
+# include $(shell pwd)/../../Makefile_test.common
+# TESTS = test1 test2
+# test1_verify = $(call diff_test,test1,ext) && test $$(grep "PASS" test1/test1.txt | wc -l) -eq 2
+# test2_verify = $(call diff_test,test2,ext)
+#
+define test_tpl =
+$(1): $(1)/ok
+ @$$($(1)_verify); \
+ RETVAL=$$$$? ; \
+ if [ $$$$RETVAL -eq 0 ]; then \
+ echo "Test $(1) PASSED"; \
+ touch $$<; \
+ true; \
+ else \
+ echo "Test $(1) FAILED"; \
+ false; \
+ fi
+
+$(1)/ok: $(1)/$(1).v
+ @echo "Running test $(1)"
+ @cd $(1); \
+ DESIGN_TOP=$(1) \
+ yosys -c $(1).tcl -q -l $(1).log
+
+endef
+
+diff_test = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
+
+all: $(TESTS)
+.PHONY: all clean $(TESTS)
+
+$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
+
+clean:
+ @rm -rf $(foreach test,$(TESTS),$(test)/$(test).sdc $(test)/$(test).txt $(test)/$(test).eblif $(test)/$(test).json)
+ @find . -name "ok" -or -name "*.log" | xargs rm -rf
diff --git a/fasm-plugin/tests/Makefile b/fasm-plugin/tests/Makefile
index f5ddc62..320dfcf 100644
--- a/fasm-plugin/tests/Makefile
+++ b/fasm-plugin/tests/Makefile
@@ -1,6 +1 @@
-TESTS = dummy
-
-all: $(TESTS)
-
-dummy:
- @echo $@ PASS
+include $(shell pwd)/../../Makefile_test.common
diff --git a/get_count-plugin/tests/Makefile b/get_count-plugin/tests/Makefile
index 80cdc79..676689e 100644
--- a/get_count-plugin/tests/Makefile
+++ b/get_count-plugin/tests/Makefile
@@ -1,15 +1,5 @@
-TESTS = $(subst /, ,$(wildcard */))
+TESTS = simple
-all: clean $(addsuffix /ok,$(TESTS))
+include $(shell pwd)/../../Makefile_test.common
-clean:
- @find . -name "ok" | xargs rm -rf
-
-define maketest =
-$1/ok:
- cd $1 && $(MAKE) test
-endef
-
-$(foreach _,${TESTS},$(eval $(call maketest,$_)))
-
-.PHONY: all clean
+simple_verify = true
diff --git a/get_count-plugin/tests/simple/script.tcl b/get_count-plugin/tests/simple/simple.tcl
similarity index 93%
rename from get_count-plugin/tests/simple/script.tcl
rename to get_count-plugin/tests/simple/simple.tcl
index e21a36d..f933c94 100644
--- a/get_count-plugin/tests/simple/script.tcl
+++ b/get_count-plugin/tests/simple/simple.tcl
@@ -1,7 +1,7 @@
yosys plugin -i get_count
yosys -import
-read_verilog -icells design.v
+read_verilog -icells simple.v
hierarchy -auto-top
set n [get_count -modules my_gate]
diff --git a/get_count-plugin/tests/simple/design.v b/get_count-plugin/tests/simple/simple.v
similarity index 100%
rename from get_count-plugin/tests/simple/design.v
rename to get_count-plugin/tests/simple/simple.v
diff --git a/params-plugin/tests/Makefile b/params-plugin/tests/Makefile
index a3f2ff3..eceb128 100644
--- a/params-plugin/tests/Makefile
+++ b/params-plugin/tests/Makefile
@@ -1,39 +1,12 @@
TESTS = pll
+include $(shell pwd)/../../Makefile_test.common
-pll_verify = $(call compare_json,pll) && test $$(grep "PASS" pll/params.txt | wc -l) -eq 2
+json_test = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
-all: $(TESTS)
-
-compare_json = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
-
-define test_tpl =
-$(1): $(1)/$(1).json
- $$($(1)_verify)
- RETVAL=$$$$? ; \
- if [ $$$$RETVAL -eq 0 ]; then \
- echo "$(1) PASS"; \
- true; \
- else \
- echo "$(1) FAIL"; \
- false; \
- fi
-
-$(1)/$(1).json: $(1)/$(1).v
- cd $(1); \
- PART_JSON=../xc7a35tcsg324-1.json \
- OUT_JSON=$(1).json \
- INPUT_XDC_FILE=$(1).xdc \
- yosys -p "tcl $(1).tcl" $(1).v -l yosys.log
-
-update_$(1): $(1)/$(1).json
- @python compare_output_json.py --json $$< --golden $(1)/$(1).golden.json --update
-
+define json_update =
+$(1)_update_json:
+ python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json --update
endef
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
+pll_verify = $(call json_test,pll) && test $$(grep "PASS" pll/pll.txt | wc -l) -eq 2
-update: $(foreach test,$(TESTS),update_$(test))
-
-
-clean:
- rm -rf $(foreach test,$(TESTS),$(test)/$(test).json $(test)/$(test).eblif $(test)/$(test).txt $(test)/yosys.log)
diff --git a/params-plugin/tests/pll/pll.tcl b/params-plugin/tests/pll/pll.tcl
index f6a6bf8..cc6e7b3 100644
--- a/params-plugin/tests/pll/pll.tcl
+++ b/params-plugin/tests/pll/pll.tcl
@@ -4,6 +4,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -14,7 +15,7 @@
if {[llength $phase] != 2} {
error "Getparam should return a list with 2 elements"
}
-set fp [open "params.txt" "w"]
+set fp [open "pll.txt" "w"]
puts -nonewline $fp "Phase before: "
if {$phase == $reference_phase} {
puts $fp "PASS"
@@ -25,7 +26,7 @@
# Modify the phase parameter value on one of the PLLE2_ADV instances
setparam -set CLKOUT2_PHASE [expr [lindex $phase 0] * 1000] top/PLLE2_ADV
-# Verify that the parameter has been correctly updated on the chosen instance
+# Verify that the parameter has been correctly updated on the chosen instance
set reference_phase [list 90000 70]
set phase [getparam CLKOUT2_PHASE top/PLLE2_ADV_0 top/PLLE2_ADV]
puts -nonewline $fp "Phase after: "
@@ -40,8 +41,8 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
# Map Xilinx tech library to 7-series VPR tech library.
-read_verilog -lib ../techmaps/cells_sim.v
-techmap -map ../techmaps/cells_map.v
+read_verilog -lib ./techmaps/cells_sim.v
+techmap -map ./techmaps/cells_map.v
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
@@ -52,5 +53,5 @@
stat
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
write_blif -attr -param -cname -conn pll.eblif
diff --git a/params-plugin/tests/techmaps/cells_map.v b/params-plugin/tests/pll/techmaps/cells_map.v
similarity index 100%
rename from params-plugin/tests/techmaps/cells_map.v
rename to params-plugin/tests/pll/techmaps/cells_map.v
diff --git a/params-plugin/tests/techmaps/cells_sim.v b/params-plugin/tests/pll/techmaps/cells_sim.v
similarity index 100%
rename from params-plugin/tests/techmaps/cells_sim.v
rename to params-plugin/tests/pll/techmaps/cells_sim.v
diff --git a/params-plugin/tests/xc7a35tcsg324-1.json b/params-plugin/tests/xc7a35tcsg324-1.json
deleted file mode 100644
index 602b949..0000000
--- a/params-plugin/tests/xc7a35tcsg324-1.json
+++ /dev/null
@@ -1,10 +0,0 @@
-{
- "iobanks": {
- "0": "X1Y78",
- "14": "X1Y26",
- "15": "X1Y78",
- "16": "X1Y130",
- "34": "X113Y26",
- "35": "X113Y78"
- }
-}
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 718241c..b2d146a 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,7 +1,6 @@
# counter, counter2, pll - test buffer and clock divider propagation
# set_false_path - test the set_false_path command
# set_max_delay - test the set_max_delay command
-
TESTS = counter \
counter2 \
pll \
@@ -10,42 +9,13 @@
pll_approx_equal \
set_false_path \
set_max_delay
+include $(shell pwd)/../../Makefile_test.common
-.PHONY: $(TESTS)
-
-counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
-counter2_verify = $(call compare,counter2,sdc) && $(call compare,counter2,txt)
-pll_verify = $(call compare,pll,sdc)
-pll_div_verify = $(call compare,pll_div,sdc)
-pll_fbout_phase_verify = $(call compare,pll_fbout_phase,sdc)
-pll_approx_equal_verify = $(call compare,pll_approx_equal,sdc)
-set_false_path_verify = $(call compare,set_false_path,sdc)
-set_max_delay_verify = $(call compare,set_max_delay,sdc)
-
-all: $(TESTS)
-compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
-
-define test_tpl =
-$(1): $(1)/$(1).sdc
- $$($(1)_verify)
- RETVAL=$$$$? ; \
- if [ $$$$RETVAL -eq 0 ]; then \
- echo "$(1) PASS"; \
- true; \
- else \
- echo "$(1) FAIL"; \
- false; \
- fi
-
-$(1)/$(1).sdc: $(1)/$(1).v
- cd $(1); \
- INPUT_SDC_FILE=$(1).input.sdc \
- OUTPUT_SDC_FILE=$(1).sdc \
- yosys -p "tcl $(1).tcl" -l yosys.log
-
-endef
-
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
-
-clean:
- rm -rf $(foreach test,$(TESTS),$(test)/$(test).sdc $(test)/$(test).txt $(test)/yosys.log)
+counter_verify = $(call diff_test,counter,sdc) && $(call diff_test,counter,txt)
+counter2_verify = $(call diff_test,counter2,sdc) && $(call diff_test,counter2,txt)
+pll_verify = $(call diff_test,pll,sdc)
+pll_div_verify = $(call diff_test,pll_div,sdc)
+pll_fbout_phase_verify = $(call diff_test,pll_fbout_phase,sdc)
+pll_approx_equal_verify = $(call diff_test,pll_approx_equal,sdc)
+set_false_path_verify = $(call diff_test,set_false_path,sdc)
+set_max_delay_verify = $(call diff_test,set_max_delay,sdc)
diff --git a/sdc-plugin/tests/counter/counter.tcl b/sdc-plugin/tests/counter/counter.tcl
index a27caf9..4fcf9be 100644
--- a/sdc-plugin/tests/counter/counter.tcl
+++ b/sdc-plugin/tests/counter/counter.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog counter.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -11,16 +11,16 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design's timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write the clocks to file
-set fh [open counter.txt w]
+set fh [open $::env(DESIGN_TOP).txt w]
set clocks [get_clocks]
puts $fh $clocks
close $fh
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/counter2/counter2.tcl b/sdc-plugin/tests/counter2/counter2.tcl
index 80bce1b..4fcf9be 100644
--- a/sdc-plugin/tests/counter2/counter2.tcl
+++ b/sdc-plugin/tests/counter2/counter2.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog counter2.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -11,16 +11,16 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design's timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write the clocks to file
-set fh [open counter2.txt w]
+set fh [open $::env(DESIGN_TOP).txt w]
set clocks [get_clocks]
puts $fh $clocks
close $fh
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl
index 61e67f6..5a2e3c4 100644
--- a/sdc-plugin/tests/pll/pll.tcl
+++ b/sdc-plugin/tests/pll/pll.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog pll.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -12,10 +12,10 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
index 13c8890..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
+++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog pll_approx_equal.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -12,10 +12,10 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl
index f8f0a9f..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_div/pll_div.tcl
+++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog pll_div.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -12,10 +12,10 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
index 6b6db73..5a2e3c4 100644
--- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
+++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
@@ -3,7 +3,7 @@
# Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog pll_fbout_phase.v
+read_verilog $::env(DESIGN_TOP).v
read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
hierarchy -check -auto-top
@@ -12,10 +12,10 @@
synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
# Read the design timing constraints
-read_sdc $::env(INPUT_SDC_FILE)
+read_sdc $::env(DESIGN_TOP).input.sdc
# Propagate the clocks
propagate_clocks
# Write out the SDC file after the clock propagation step
-write_sdc $::env(OUTPUT_SDC_FILE)
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl
index 39a51c0..a4e01f4 100644
--- a/sdc-plugin/tests/set_false_path/set_false_path.tcl
+++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog set_false_path.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
@@ -16,4 +16,4 @@
# -from clk to bottom_inst/I
set_false_path -from clk -to bottom_inst.I
-write_sdc set_false_path.sdc
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
index 8cfde6a..f2a5b4f 100644
--- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -3,7 +3,7 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
-read_verilog set_max_delay.v
+read_verilog $::env(DESIGN_TOP).v
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
@@ -16,4 +16,4 @@
# -from clk to bottom_inst/I
set_max_delay 3 -from clk -to bottom_inst.I
-write_sdc set_max_delay.sdc
+write_sdc $::env(DESIGN_TOP).sdc
diff --git a/selection-plugin/tests/Makefile b/selection-plugin/tests/Makefile
index e29a406..e203741 100644
--- a/selection-plugin/tests/Makefile
+++ b/selection-plugin/tests/Makefile
@@ -1,32 +1,3 @@
TESTS = counter
-.PHONY: $(TESTS)
-
-counter_verify = $(call compare,counter,txt)
-
-all: $(TESTS)
-compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
-
-define test_tpl =
-$(1): $(1)/$(1).txt
- $$($(1)_verify)
- RETVAL=$$$$? ; \
- if [ $$$$RETVAL -eq 0 ]; then \
- echo "$(1) PASS"; \
- true; \
- else \
- echo "$(1) FAIL"; \
- false; \
- fi
-
-$(1)/$(1).txt: $(1)/$(1).v
- cd $(1); \
- INPUT_SDC_FILE=$(1).input.sdc \
- OUTPUT_SDC_FILE=$(1).sdc \
- yosys -p "tcl $(1).tcl" -l yosys.log
-
-endef
-
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
-
-clean:
- rm -rf $(foreach test,$(TESTS),$(test)/$(test).sdc $(test)/$(test).txt $(test)/yosys.log)
+include $(shell pwd)/../../Makefile_test.common
+counter_verify = $(call diff_test,counter,txt)
diff --git a/xdc-plugin/tests/Makefile b/xdc-plugin/tests/Makefile
index 714ed73..76d2241 100644
--- a/xdc-plugin/tests/Makefile
+++ b/xdc-plugin/tests/Makefile
@@ -3,51 +3,23 @@
# io_loc_pairs - test for LOC property being set on IOBUFs as the IO_LOC_PAIRS parameter
# minilitex_ddr_arty - litex design with more types of IOBUFS including differential
# package_pins - test for PACKAGE_PIN property being set on IOBUFs as the IO_LOC_PAIRS parameter
-
TESTS = counter \
port_indexes \
io_loc_pairs \
minilitex_ddr_arty \
package_pins
-counter_verify = $(call compare_json,counter)
-port_indexes_verify = $(call compare_json,port_indexes) && test $$(grep "'unknown' proc command handler" port_indexes/port_indexes.txt | wc -l) -eq 2
-io_loc_pairs_verify = $(call compare_json,io_loc_pairs)
-minilitex_ddr_arty_verify = $(call compare_json,minilitex_ddr_arty)
-package_pins_verify = $(call compare_json,package_pins)
+include $(shell pwd)/../../Makefile_test.common
-all: $(TESTS)
+json_test = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
-compare_json = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1)_golden.json
-
-define test_tpl =
-$(1): $(1)/$(1).json
- $$($(1)_verify)
- RETVAL=$$$$? ; \
- if [ $$$$RETVAL -eq 0 ]; then \
- echo "$(1) PASS"; \
- true; \
- else \
- echo "$(1) FAIL"; \
- false; \
- fi
-
-$(1)/$(1).json: $(1)/$(1).v
- cd $(1); \
- PART_JSON=../xc7a35tcsg324-1.json \
- OUT_JSON=$(1).json \
- INPUT_XDC_FILE=$(1).xdc \
- yosys -p "tcl $(1).tcl" $(1).v -l yosys.log
-
-update_$(1): $(1)/$(1).json
- @python compare_output_json.py --json $$< --golden $(1)/$(1)_golden.json --update
-
+define json_update =
+$(1)_update_json:
+ python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json --update
endef
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
-
-update: $(foreach test,$(TESTS),update_$(test))
-
-
-clean:
- rm -rf $(foreach test,$(TESTS),$(test)/$(test).json $(test)/$(test).eblif $(test)/$(test).txt $(test)/yosys.log)
+counter_verify = $(call json_test,counter)
+port_indexes_verify = $(call json_test,port_indexes) && test $$(grep "'unknown' proc command handler" port_indexes/port_indexes.txt | wc -l) -eq 2
+io_loc_pairs_verify = $(call json_test,io_loc_pairs)
+minilitex_ddr_arty_verify = $(call json_test,minilitex_ddr_arty)
+package_pins_verify = $(call json_test,package_pins)
diff --git a/xdc-plugin/tests/counter/counter_golden.json b/xdc-plugin/tests/counter/counter.golden.json
similarity index 100%
rename from xdc-plugin/tests/counter/counter_golden.json
rename to xdc-plugin/tests/counter/counter.golden.json
diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl
index 696dc4d..b7090c8 100644
--- a/xdc-plugin/tests/counter/counter.tcl
+++ b/xdc-plugin/tests/counter/counter.tcl
@@ -2,12 +2,15 @@
plugin -i xdc
#Import the commands from the plugins to the tcl interpreter
yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
+
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs_golden.json b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.golden.json
similarity index 100%
rename from xdc-plugin/tests/io_loc_pairs/io_loc_pairs_golden.json
rename to xdc-plugin/tests/io_loc_pairs/io_loc_pairs.golden.json
diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
index 8c0a57c..b7090c8 100644
--- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
+++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
@@ -3,12 +3,14 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
+read_verilog $::env(DESIGN_TOP).v
+
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty_golden.json b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.golden.json
similarity index 100%
rename from xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty_golden.json
rename to xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.golden.json
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
index 9597cd4..af91ce6 100644
--- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
+++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
@@ -2,14 +2,15 @@
plugin -i xdc
#Import the commands from the plugins to the tcl interpreter
yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
read_verilog VexRiscv_Lite.v
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
-write_blif -attr -param -cname -conn counter.eblif
+write_json $::env(DESIGN_TOP).json
diff --git a/xdc-plugin/tests/package_pins/package_pins_golden.json b/xdc-plugin/tests/package_pins/package_pins.golden.json
similarity index 100%
rename from xdc-plugin/tests/package_pins/package_pins_golden.json
rename to xdc-plugin/tests/package_pins/package_pins.golden.json
diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl
index 8c0a57c..66bd21d 100644
--- a/xdc-plugin/tests/package_pins/package_pins.tcl
+++ b/xdc-plugin/tests/package_pins/package_pins.tcl
@@ -3,12 +3,13 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
+read_verilog $::env(DESIGN_TOP).v
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
diff --git a/xdc-plugin/tests/port_indexes/port_indexes_golden.json b/xdc-plugin/tests/port_indexes/port_indexes.golden.json
similarity index 100%
rename from xdc-plugin/tests/port_indexes/port_indexes_golden.json
rename to xdc-plugin/tests/port_indexes/port_indexes.golden.json
diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl
index ac05de3..ed35c69 100644
--- a/xdc-plugin/tests/port_indexes/port_indexes.tcl
+++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl
@@ -3,6 +3,8 @@
#Import the commands from the plugins to the tcl interpreter
yosys -import
+read_verilog $::env(DESIGN_TOP).v
+
# -flatten is used to ensure that the output eblif has only one module.
# Some of symbiflow expects eblifs with only one module.
synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
@@ -19,7 +21,7 @@
puts $fp $result
}
#Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
if {[catch {invalid command} result]} {
close $fp
@@ -30,4 +32,4 @@
close $fp
# Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json
