diff --git a/dsp_ff-plugin/dsp_ff.cc b/dsp_ff-plugin/dsp_ff.cc
index 1a2c0a9..eb7b449 100644
--- a/dsp_ff-plugin/dsp_ff.cc
+++ b/dsp_ff-plugin/dsp_ff.cc
@@ -11,22 +11,17 @@
 
     /// A structure identifying specific pin in a cell instance
     struct CellPin {
-        RTLIL::Cell*    cell;   /// Cell pointer (nullptr for top-level ports)
-        RTLIL::IdString port;   /// Port name
-        int             bit;    /// Bit index
+        RTLIL::Cell *cell;    /// Cell pointer (nullptr for top-level ports)
+        RTLIL::IdString port; /// Port name
+        int bit;              /// Bit index
 
-        CellPin (RTLIL::Cell* _cell,
-                 const RTLIL::IdString& _port,
-                 int _bit = 0) : 
-            cell(_cell),
-            port(_port),
-            bit (_bit)
-        {}
+        CellPin(RTLIL::Cell *_cell, const RTLIL::IdString &_port, int _bit = 0) : cell(_cell), port(_port), bit(_bit) {}
 
-        CellPin (const CellPin& ref) = default;
-        CellPin (CellPin&& ref) = default;
+        CellPin(const CellPin &ref) = default;
+        CellPin(CellPin &&ref) = default;
 
-        unsigned int hash () const {
+        unsigned int hash() const
+        {
             unsigned int h = 0;
             if (cell != nullptr) {
                 h = mkhash_add(h, cell->hash());
@@ -36,25 +31,14 @@
             return h;
         }
 
-        bool operator == (const CellPin& ref) const {
-            return  (cell == ref.cell) &&
-                    (port == ref.port) &&
-                    (bit  == ref.bit);
-        }
+        bool operator==(const CellPin &ref) const { return (cell == ref.cell) && (port == ref.port) && (bit == ref.bit); }
 
-        std::string as_string () const {
+        std::string as_string() const
+        {
             if (cell != nullptr) {
-                return stringf("%s.%s[%d]",
-                    RTLIL::unescape_id(cell->name).c_str(),
-                    RTLIL::unescape_id(port).c_str(),
-                    bit
-                );
-            }
-            else {
-                return stringf("%s[%d]",
-                    RTLIL::unescape_id(port).c_str(),
-                    bit
-                );
+                return stringf("%s.%s[%d]", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(port).c_str(), bit);
+            } else {
+                return stringf("%s[%d]", RTLIL::unescape_id(port).c_str(), bit);
             }
         }
     };
@@ -93,7 +77,7 @@
 
         struct {
             /// A dict of parameters to be set in the cell after integration
-            dict<RTLIL::IdString, RTLIL::Const>    set;
+            dict<RTLIL::IdString, RTLIL::Const> set;
             /// A dict of parameters to be mapped to the cell after integration
             dict<RTLIL::IdString, RTLIL::IdString> map;
         } params;
@@ -113,8 +97,8 @@
 
     /// Describes a changes made to a DSP cell
     struct DspChanges {
-        pool<RTLIL::IdString>  params; // Modified params
-        pool<RTLIL::IdString>  conns;  // Altered connections (ports)
+        pool<RTLIL::IdString> params; // Modified params
+        pool<RTLIL::IdString> conns;  // Altered connections (ports)
     };
 
     // ..........................................
@@ -128,12 +112,13 @@
             dict<RTLIL::IdString, RTLIL::Const> dsp;
         } params;
 
-        FlopData (const RTLIL::IdString& _type) : type(_type) {};
+        FlopData(const RTLIL::IdString &_type) : type(_type){};
 
-        FlopData (const FlopData& ref) = default;
-        FlopData (FlopData&& ref) = default;
+        FlopData(const FlopData &ref) = default;
+        FlopData(FlopData &&ref) = default;
 
-        unsigned int hash () const {
+        unsigned int hash() const
+        {
             unsigned int h = 0;
             h = mkhash_add(h, type.hash());
             h = mkhash_add(h, conns.hash());
@@ -142,25 +127,21 @@
             return h;
         }
 
-        bool operator == (const FlopData& ref) const {
-            return  (type == ref.type) &&
-                    (conns == ref.conns) &&
-                    (params.flop == ref.params.flop) &&
-                    (params.dsp == ref.params.dsp);
+        bool operator==(const FlopData &ref) const
+        {
+            return (type == ref.type) && (conns == ref.conns) && (params.flop == ref.params.flop) && (params.dsp == ref.params.dsp);
         }
     };
 
     // ..........................................
 
     /// Loads FF and DSP integration rules from a file
-    void load_rules(const std::string& a_FileName) {
+    void load_rules(const std::string &a_FileName)
+    {
 
         // Parses a string and returns a vector of fields delimited by the
         // given character.
-        auto getFields = [](const std::string& a_String,
-                             const char a_Delim = ' ',
-                             bool a_KeepEmpty = false)
-        {
+        auto getFields = [](const std::string &a_String, const char a_Delim = ' ', bool a_KeepEmpty = false) {
             std::vector<std::string> fields;
             std::stringstream ss(a_String);
 
@@ -177,17 +158,16 @@
 
         // Parses a vector of strings like "<name>=<value>" starting from the
         // second one on the list
-        auto parseNameValue = [&](const std::vector<std::string>& strs) {
-            const std::regex expr ("(\\S+)=(\\S+)");
-            std::smatch      match;
+        auto parseNameValue = [&](const std::vector<std::string> &strs) {
+            const std::regex expr("(\\S+)=(\\S+)");
+            std::smatch match;
 
             std::vector<std::pair<std::string, std::string>> vec;
 
-            for (size_t i=1; i<strs.size(); ++i) {
+            for (size_t i = 1; i < strs.size(); ++i) {
                 if (std::regex_match(strs[i], match, expr)) {
                     vec.push_back(std::make_pair(match[1], match[2]));
-                }
-                else {
+                } else {
                     log_error(" syntax error: '%s'\n", strs[i].c_str());
                 }
             }
@@ -196,33 +176,26 @@
         };
 
         // Parses port name as "<name>[<hi>:<lo>]" or just "<name>"
-        auto parsePortName = [&](const std::string& str) {
-            const std::regex expr ("^(.*)\\[([0-9]+):([0-9]+)\\]");
-            std::smatch      match;
+        auto parsePortName = [&](const std::string &str) {
+            const std::regex expr("^(.*)\\[([0-9]+):([0-9]+)\\]");
+            std::smatch match;
 
             std::tuple<std::string, int, int> data;
             auto res = std::regex_match(str, match, expr);
             if (res) {
-                data = std::make_tuple(
-                    std::string(match[1]),
-                    std::stoi(match[2]),
-                    std::stoi(match[3])
-                );
-    
-                if ((std::get<2>(data) > std::get<1>(data)) ||
-                    std::get<2>(data) < 0 || std::get<1>(data) < 0)
-                {
+                data = std::make_tuple(std::string(match[1]), std::stoi(match[2]), std::stoi(match[3]));
+
+                if ((std::get<2>(data) > std::get<1>(data)) || std::get<2>(data) < 0 || std::get<1>(data) < 0) {
                     log_error(" invalid port spec: '%s'\n", str.c_str());
                 }
-            }
-            else {
+            } else {
                 data = std::make_tuple(str, -1, -1);
             }
 
             return data;
         };
 
-        std::ifstream file (a_FileName);
+        std::ifstream file(a_FileName);
         std::string line;
 
         log("Loading rules from '%s'...\n", a_FileName.c_str());
@@ -230,8 +203,8 @@
             log_error(" Error opening file!\n");
         }
 
-        std::vector<DspType>    dspTypes;
-        std::vector<FlopType>   flopTypes;
+        std::vector<DspType> dspTypes;
+        std::vector<FlopType> flopTypes;
 
         std::vector<RTLIL::IdString> dspAliases;
 
@@ -269,15 +242,14 @@
                 }
                 tok.push_back(fields[0]);
 
-                dspTypes.resize(dspTypes.size() + 1);\
+                dspTypes.resize(dspTypes.size() + 1);
                 dspTypes.back().name = RTLIL::escape_id(fields[1]);
 
                 dspAliases.clear();
-                for (size_t i=2; i<fields.size(); ++i) {
+                for (size_t i = 2; i < fields.size(); ++i) {
                     dspAliases.push_back(RTLIL::escape_id(fields[i]));
                 }
-            }
-            else if (fields[0] == "enddsp") {
+            } else if (fields[0] == "enddsp") {
                 if (fields.size() != 1) {
                     log_error(" syntax error: '%s'\n", line.c_str());
                 }
@@ -287,7 +259,7 @@
                 tok.pop_back();
 
                 const auto dspType = dspTypes.back();
-                for (const auto& alias : dspAliases) {
+                for (const auto &alias : dspAliases) {
                     dspTypes.push_back(dspType);
                     dspTypes.back().name = alias;
                 }
@@ -305,25 +277,21 @@
 
                 auto spec = parsePortName(fields[1]);
 
-                auto& ports = dspTypes.back().ports;
+                auto &ports = dspTypes.back().ports;
                 ports.resize(ports.size() + 1);
                 ports.back().name = RTLIL::escape_id(std::get<0>(spec));
                 ports.back().bits = std::make_pair(std::get<2>(spec), std::get<1>(spec));
-                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("clk"),
-                    std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
-                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("rst"),
-                    std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
-                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("ena"),
-                    std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
-            }
-            else if (fields[0] == "endport") {
+                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("clk"), std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
+                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("rst"), std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
+                ports.back().assoc.insert(std::make_pair(RTLIL::escape_id("ena"), std::make_pair(RTLIL::IdString(), RTLIL::Sx)));
+            } else if (fields[0] == "endport") {
                 if (fields.size() != 1) {
                     log_error(" syntax error: '%s'\n", line.c_str());
                 }
                 if (tok.size() != 2 || tok.back() != "port") {
                     log_error(" unexpected keyword '%s'\n", fields[0].c_str());
                 }
-                tok.pop_back(); 
+                tok.pop_back();
             }
 
             // Flip-flop type section
@@ -338,25 +306,19 @@
 
                 flopTypes.resize(flopTypes.size() + 1);
                 flopTypes.back().name = RTLIL::escape_id(fields[1]);
-                flopTypes.back().ports.insert(std::make_pair(
-                    RTLIL::escape_id("clk"), RTLIL::IdString()));
-                flopTypes.back().ports.insert(std::make_pair(
-                    RTLIL::escape_id("rst"), RTLIL::IdString()));
-                flopTypes.back().ports.insert(std::make_pair(
-                    RTLIL::escape_id("ena"), RTLIL::IdString()));
-                flopTypes.back().ports.insert(std::make_pair(
-                    RTLIL::escape_id("d"),   RTLIL::IdString()));
-                flopTypes.back().ports.insert(std::make_pair(
-                    RTLIL::escape_id("q"),   RTLIL::IdString()));
-            }
-            else if (fields[0] == "endff") {
+                flopTypes.back().ports.insert(std::make_pair(RTLIL::escape_id("clk"), RTLIL::IdString()));
+                flopTypes.back().ports.insert(std::make_pair(RTLIL::escape_id("rst"), RTLIL::IdString()));
+                flopTypes.back().ports.insert(std::make_pair(RTLIL::escape_id("ena"), RTLIL::IdString()));
+                flopTypes.back().ports.insert(std::make_pair(RTLIL::escape_id("d"), RTLIL::IdString()));
+                flopTypes.back().ports.insert(std::make_pair(RTLIL::escape_id("q"), RTLIL::IdString()));
+            } else if (fields[0] == "endff") {
                 if (fields.size() != 1) {
                     log_error(" syntax error: '%s'\n", line.c_str());
                 }
                 if (tok.size() != 1 || tok.back() != "ff") {
                     log_error(" unexpected keyword '%s'\n", fields[0].c_str());
                 }
-                tok.pop_back(); 
+                tok.pop_back();
             }
 
             // Signals
@@ -370,20 +332,15 @@
                     if (fields.size() != 3) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
-                    auto& ports = dspTypes.back().ports;
-                    ports.back().assoc[RTLIL::escape_id("clk")] = std::make_pair(
-                        RTLIL::escape_id(fields[1]),
-                        RTLIL::Const::from_string(fields[2])
-                    );
-                }
-                else if (tok.back() == "ff") {
+                    auto &ports = dspTypes.back().ports;
+                    ports.back().assoc[RTLIL::escape_id("clk")] = std::make_pair(RTLIL::escape_id(fields[1]), RTLIL::Const::from_string(fields[2]));
+                } else if (tok.back() == "ff") {
                     if (fields.size() != 2) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
                     flopTypes.back().ports[RTLIL::escape_id("clk")] = RTLIL::escape_id(fields[1]);
                 }
-            }
-            else if (fields[0] == "rst") {
+            } else if (fields[0] == "rst") {
                 if (tok.size() == 0 || (tok.back() != "port" && tok.back() != "ff")) {
                     log_error(" unexpected keyword '%s'\n", fields[0].c_str());
                 }
@@ -393,20 +350,15 @@
                     if (fields.size() != 3) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
-                    auto& ports = dspTypes.back().ports;
-                    ports.back().assoc[RTLIL::escape_id("rst")] = std::make_pair(
-                        RTLIL::escape_id(fields[1]),
-                        RTLIL::Const::from_string(fields[2])
-                    );
-                }
-                else if (tok.back() == "ff") {
+                    auto &ports = dspTypes.back().ports;
+                    ports.back().assoc[RTLIL::escape_id("rst")] = std::make_pair(RTLIL::escape_id(fields[1]), RTLIL::Const::from_string(fields[2]));
+                } else if (tok.back() == "ff") {
                     if (fields.size() != 2) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
                     flopTypes.back().ports[RTLIL::escape_id("rst")] = RTLIL::escape_id(fields[1]);
                 }
-            }
-            else if (fields[0] == "ena") {
+            } else if (fields[0] == "ena") {
                 if (tok.size() == 0 || (tok.back() != "port" && tok.back() != "ff")) {
                     log_error(" unexpected keyword '%s'\n", fields[0].c_str());
                 }
@@ -416,13 +368,9 @@
                     if (fields.size() != 3) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
-                    auto& ports = dspTypes.back().ports;
-                    ports.back().assoc[RTLIL::escape_id("ena")] = std::make_pair(
-                        RTLIL::escape_id(fields[1]),
-                        RTLIL::Const::from_string(fields[2])
-                    );
-                }
-                else if (tok.back() == "ff") {
+                    auto &ports = dspTypes.back().ports;
+                    ports.back().assoc[RTLIL::escape_id("ena")] = std::make_pair(RTLIL::escape_id(fields[1]), RTLIL::Const::from_string(fields[2]));
+                } else if (tok.back() == "ff") {
                     if (fields.size() != 2) {
                         log_error(" syntax error: '%s'\n", line.c_str());
                     }
@@ -439,8 +387,7 @@
                 }
 
                 flopTypes.back().ports[RTLIL::escape_id("d")] = RTLIL::escape_id(fields[1]);
-            }
-            else if (fields[0] == "q") {
+            } else if (fields[0] == "q") {
                 if (fields.size() != 2) {
                     log_error(" syntax error: '%s'\n", line.c_str());
                 }
@@ -460,7 +407,7 @@
                     log_error(" unexpected keyword '%s'\n", fields[0].c_str());
                 }
 
-                for (size_t i=1; i<fields.size(); ++i) {
+                for (size_t i = 1; i < fields.size(); ++i) {
                     flopTypes.back().params.matching.push_back(RTLIL::escape_id(fields[i]));
                 }
             }
@@ -475,18 +422,14 @@
 
                 const auto vec = parseNameValue(fields);
                 dict<RTLIL::IdString, RTLIL::Const> set;
-                for (const auto& it : vec) {
-                    set.insert(std::make_pair(
-                        RTLIL::escape_id(it.first),
-                        RTLIL::Const(it.second)
-                    ));
+                for (const auto &it : vec) {
+                    set.insert(std::make_pair(RTLIL::escape_id(it.first), RTLIL::Const(it.second)));
                 }
 
                 if (tok.back() == "port") {
-                    auto& ports = dspTypes.back().ports;
+                    auto &ports = dspTypes.back().ports;
                     ports.back().params.set.swap(set);
-                }
-                else if (tok.back() == "ff") {
+                } else if (tok.back() == "ff") {
                     flopTypes.back().params.set.swap(set);
                 }
             }
@@ -501,18 +444,14 @@
 
                 const auto vec = parseNameValue(fields);
                 dict<RTLIL::IdString, RTLIL::IdString> map;
-                for (const auto& it : vec) {
-                    map.insert(std::make_pair(
-                        RTLIL::escape_id(it.first),
-                        RTLIL::escape_id(it.second)
-                    ));
+                for (const auto &it : vec) {
+                    map.insert(std::make_pair(RTLIL::escape_id(it.first), RTLIL::escape_id(it.second)));
                 }
 
                 if (tok.back() == "port") {
-                    auto& ports = dspTypes.back().ports;
+                    auto &ports = dspTypes.back().ports;
                     ports.back().params.map.swap(map);
-                }
-                else if (tok.back() == "ff") {
+                } else if (tok.back() == "ff") {
                     flopTypes.back().params.map.swap(map);
                 }
             }
@@ -526,12 +465,9 @@
                 }
 
                 const auto vec = parseNameValue(fields);
-                auto& ports = dspTypes.back().ports;
-                for (const auto& it : vec) {
-                    ports.back().connect.insert(std::make_pair(
-                        RTLIL::escape_id(it.first),
-                        RTLIL::Const(it.second)
-                    ));
+                auto &ports = dspTypes.back().ports;
+                for (const auto &it : vec) {
+                    ports.back().connect.insert(std::make_pair(RTLIL::escape_id(it.first), RTLIL::Const(it.second)));
                 }
             }
 
@@ -541,30 +477,31 @@
         }
 
         // Convert lists to maps
-        for (const auto& it : dspTypes) {
+        for (const auto &it : dspTypes) {
             if (m_DspTypes.count(it.name)) {
                 log_error(" duplicated rule for DSP '%s'\n", it.name.c_str());
             }
             m_DspTypes.insert(std::make_pair(it.name, it));
         }
-        for (const auto& it : flopTypes) {
+        for (const auto &it : flopTypes) {
             if (m_FlopTypes.count(it.name)) {
                 log_error(" duplicated rule for flip-flop '%s'\n", it.name.c_str());
             }
             m_FlopTypes.insert(std::make_pair(it.name, it));
         }
-    } 
+    }
 
-    void dump_rules() {
+    void dump_rules()
+    {
 
         // Dump DSP types
         log("DSP types:\n");
-        for (const auto& it : m_DspTypes) {
-            const auto& dsp = it.second;
+        for (const auto &it : m_DspTypes) {
+            const auto &dsp = it.second;
             log(" %s\n", dsp.name.c_str());
 
             log(" ports:\n");
-            for (const auto& port : dsp.ports) {
+            for (const auto &port : dsp.ports) {
 
                 std::string range;
                 if (port.bits.first != -1 && port.bits.second != -1) {
@@ -573,25 +510,25 @@
 
                 log("  %s.%s%s\n", dsp.name.c_str(), port.name.c_str(), range.c_str());
 
-                for (const auto& it : port.assoc) {
+                for (const auto &it : port.assoc) {
                     log("   %.3s: %s\n", it.first.c_str(), !it.second.first.empty() ? it.second.first.c_str() : "<none>");
                 }
 
                 if (!port.params.set.empty()) {
                     log("   set params:\n");
-                    for (const auto& it : port.params.set) {
+                    for (const auto &it : port.params.set) {
                         log("    %s=%s\n", it.first.c_str(), it.second.decode_string().c_str());
                     }
                 }
                 if (!port.params.map.empty()) {
                     log("   map params:\n");
-                    for (const auto& it : port.params.map) {
+                    for (const auto &it : port.params.map) {
                         log("    %s=%s\n", it.first.c_str(), it.second.c_str());
                     }
                 }
                 if (!port.connect.empty()) {
                     log("   connect ports:\n");
-                    for (const auto& it : port.connect) {
+                    for (const auto &it : port.connect) {
                         log("    %s.%s=%s\n", dsp.name.c_str(), it.first.c_str(), it.second.as_string().c_str());
                     }
                 }
@@ -600,29 +537,29 @@
 
         // Dump flop types
         log("Flip-flop types:\n");
-        for (const auto& it : m_FlopTypes) {
-            const auto& ff = it.second;
+        for (const auto &it : m_FlopTypes) {
+            const auto &ff = it.second;
             log(" %s\n", ff.name.c_str());
-            
-            for (const auto& it : ff.ports) {
+
+            for (const auto &it : ff.ports) {
                 log("  %.3s: %s\n", it.first.c_str(), !it.second.empty() ? it.second.c_str() : "<none>");
             }
 
             if (!ff.params.set.empty()) {
                 log("  params that must match:\n");
-                for (const auto& it : ff.params.matching) {
+                for (const auto &it : ff.params.matching) {
                     log("   %s\n", it.c_str());
                 }
             }
             if (!ff.params.set.empty()) {
                 log("  set params:\n");
-                for (const auto& it : ff.params.set) {
+                for (const auto &it : ff.params.set) {
                     log("   %s=%s\n", it.first.c_str(), it.second.decode_string().c_str());
                 }
             }
             if (!ff.params.map.empty()) {
                 log("  map params:\n");
-                for (const auto& it : ff.params.map) {
+                for (const auto &it : ff.params.map) {
                     log("   %s=%s\n", it.first.c_str(), it.second.c_str());
                 }
             }
@@ -633,25 +570,24 @@
 
     /// Temporary SigBit to SigBit helper map.
     SigMap m_SigMap;
-//    /// Net map
-//    dict<RTLIL::SigBit, RTLIL::SigBit> m_NetMap;
+    //    /// Net map
+    //    dict<RTLIL::SigBit, RTLIL::SigBit> m_NetMap;
     /// Cells to be removed (per module!)
-    pool<RTLIL::Cell*> m_CellsToRemove;
+    pool<RTLIL::Cell *> m_CellsToRemove;
     /// DSP cells that got changed
-    dict<RTLIL::Cell*, DspChanges> m_DspChanges;
+    dict<RTLIL::Cell *, DspChanges> m_DspChanges;
 
     /// DSP types
-    dict<RTLIL::IdString, DspType>    m_DspTypes;
+    dict<RTLIL::IdString, DspType> m_DspTypes;
     /// Flip-flop types
-    dict<RTLIL::IdString, FlopType>   m_FlopTypes;
+    dict<RTLIL::IdString, FlopType> m_FlopTypes;
 
     // ..........................................
 
-    DspFF() :
-        Pass("dsp_ff", "Integrates flip-flop into DSP blocks")
-    {}
+    DspFF() : Pass("dsp_ff", "Integrates flip-flop into DSP blocks") {}
 
-    void help () override {
+    void help() override
+    {
         log("\n");
         log("    dsp_ff -rules <rules.txt> [selection]\n");
         log("\n");
@@ -659,7 +595,7 @@
         log("\n");
     }
 
-    void execute (std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
+    void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
     {
         log_header(a_Design, "Executing DSP_FF pass.\n");
 
@@ -702,8 +638,8 @@
             m_SigMap.clear();
             m_SigMap.set(module);
 
-//            // Build the net map
-//            buildNetMap(module);
+            //            // Build the net map
+            //            buildNetMap(module);
 
             // Look for DSP cells
             for (auto cell : module->cells()) {
@@ -714,13 +650,12 @@
                 }
 
                 // Check ports
-                auto& rule = m_DspTypes.at(cell->type);
-                for (auto& portRule : rule.ports) {
+                auto &rule = m_DspTypes.at(cell->type);
+                for (auto &portRule : rule.ports) {
 
                     // Sanity check
                     if (!cell->hasPort(portRule.name)) {
-                        log(" The DSP cell '%s' does not have a port named '%s'!\n",
-                            cell->type.c_str(), portRule.name.c_str());
+                        log(" The DSP cell '%s' does not have a port named '%s'!\n", cell->type.c_str(), portRule.name.c_str());
                         continue;
                     }
 
@@ -729,7 +664,7 @@
             }
 
             // Remove cells
-            for (const auto& cell : m_CellsToRemove) {
+            for (const auto &cell : m_CellsToRemove) {
                 module->remove(cell);
             }
             m_CellsToRemove.clear();
@@ -741,19 +676,19 @@
 
     // ..........................................
 
-//    void buildNetMap (RTLIL::Module* a_Module) {
-//        // TODO:
-//    }
+    //    void buildNetMap (RTLIL::Module* a_Module) {
+    //        // TODO:
+    //    }
 
-    bool checkDspPort (RTLIL::Cell* a_Cell, const DspPortType& a_PortRule) {
+    bool checkDspPort(RTLIL::Cell *a_Cell, const DspPortType &a_PortRule)
+    {
         bool isOk = true;
 
         // The cell register control parameters must not be set
-        for (const auto& it : a_PortRule.params.set) {
+        for (const auto &it : a_PortRule.params.set) {
             const auto curr = a_Cell->getParam(it.first);
             if (curr == it.second) {
-                log_debug("  the param '%s' is already set to '%s'\n",
-                    it.first.c_str(), it.second.decode_string().c_str());
+                log_debug("  the param '%s' is already set to '%s'\n", it.first.c_str(), it.second.decode_string().c_str());
                 isOk = false;
             }
         }
@@ -761,12 +696,12 @@
         return isOk;
     }
 
-    bool checkFlop (RTLIL::Cell* a_Cell) {
-        const auto& flopType = m_FlopTypes.at(a_Cell->type);
+    bool checkFlop(RTLIL::Cell *a_Cell)
+    {
+        const auto &flopType = m_FlopTypes.at(a_Cell->type);
         bool isOk = true;
 
-        log_debug("  Checking connected flip-flop '%s' of type '%s'... ",
-            a_Cell->name.c_str(), a_Cell->type.c_str());
+        log_debug("  Checking connected flip-flop '%s' of type '%s'... ", a_Cell->name.c_str(), a_Cell->type.c_str());
 
         // Must not have the "keep" attribute
         if (a_Cell->has_keep_attr()) {
@@ -775,11 +710,11 @@
         }
 
         // Check if required parameters are set as they should be
-        for (const auto& it : flopType.params.required) {
+        for (const auto &it : flopType.params.required) {
             const auto curr = a_Cell->getParam(it.first);
             if (curr != it.second) {
-                log_debug("\n   param '%s' mismatch ('%s' instead of '%s')",
-                    it.first.c_str(), curr.decode_string().c_str(), it.second.decode_string().c_str());
+                log_debug("\n   param '%s' mismatch ('%s' instead of '%s')", it.first.c_str(), curr.decode_string().c_str(),
+                          it.second.decode_string().c_str());
                 isOk = false;
             }
         }
@@ -792,21 +727,18 @@
         return isOk;
     }
 
-    
-    bool checkFlopDataAgainstDspPort (const FlopData& a_FlopData,
-                                      RTLIL::Cell* a_Cell,
-                                      const DspPortType& a_PortRule)
+    bool checkFlopDataAgainstDspPort(const FlopData &a_FlopData, RTLIL::Cell *a_Cell, const DspPortType &a_PortRule)
     {
-        const auto& flopType = m_FlopTypes.at(a_FlopData.type);
-        const auto& changes  = m_DspChanges[a_Cell];
+        const auto &flopType = m_FlopTypes.at(a_FlopData.type);
+        const auto &changes = m_DspChanges[a_Cell];
         bool isOk = true;
 
         log_debug("  Checking connected flip-flop settings against the DSP port... ");
 
         // Check control signal connections
-        for (const auto& it : a_PortRule.assoc) {
-            const auto& key  = it.first;
-            const auto& port = it.second.first;
+        for (const auto &it : a_PortRule.assoc) {
+            const auto &key = it.first;
+            const auto &port = it.second.first;
 
             SigBit conn(RTLIL::Sx);
             if (!port.empty() && a_Cell->hasPort(port)) {
@@ -826,14 +758,10 @@
             }
         }
 
-        auto checkParam = [&](const RTLIL::IdString& name,
-                              const RTLIL::Const& curr,
-                              const RTLIL::Const& next)
-        {
+        auto checkParam = [&](const RTLIL::IdString &name, const RTLIL::Const &curr, const RTLIL::Const &next) {
             if (curr != next && changes.params.count(name)) {
-                log_debug("\n   the param '%s' mismatch ('%s' instead of '%s')",
-                    name.c_str(), curr.decode_string().c_str(),
-                    next.decode_string().c_str());
+                log_debug("\n   the param '%s' mismatch ('%s' instead of '%s')", name.c_str(), curr.decode_string().c_str(),
+                          next.decode_string().c_str());
                 isOk = false;
                 return false;
             }
@@ -841,7 +769,7 @@
         };
 
         // Check parameters to be mapped (by the port rule)
-        for (const auto& it : a_PortRule.params.map) {
+        for (const auto &it : a_PortRule.params.map) {
             if (a_Cell->hasParam(it.first) && a_FlopData.params.dsp.count(it.second)) {
                 const auto curr = a_Cell->getParam(it.first);
                 const auto flop = a_FlopData.params.dsp.at(it.second);
@@ -850,15 +778,15 @@
         }
 
         // Check parameters to be set (by the port rule)
-        for (const auto& it : a_PortRule.params.set) {
+        for (const auto &it : a_PortRule.params.set) {
             if (a_Cell->hasParam(it.first)) {
                 const auto curr = a_Cell->getParam(it.first);
                 checkParam(it.first, curr, it.second);
             }
         }
-        
+
         // Check parameters to be mapped (by the flip-flop rule)
-        for (const auto& it : flopType.params.map) {
+        for (const auto &it : flopType.params.map) {
             if (a_Cell->hasParam(it.first) && a_FlopData.params.dsp.count(it.second)) {
                 const auto curr = a_Cell->getParam(it.first);
                 const auto flop = a_FlopData.params.dsp.at(it.second);
@@ -867,13 +795,13 @@
         }
 
         // Check parameters to be set (by the flip-flop rule)
-        for (const auto& it : flopType.params.set) {
+        for (const auto &it : flopType.params.set) {
             if (a_Cell->hasParam(it.first)) {
                 const auto curr = a_Cell->getParam(it.first);
                 checkParam(it.first, curr, it.second);
             }
         }
-        
+
         if (isOk) {
             log_debug("Ok\n");
         } else {
@@ -883,19 +811,25 @@
     }
 
     /// Returns a string with either wire name or constant value for a SigBit
-    static std::string sigBitName (const RTLIL::SigBit& a_SigBit) {
+    static std::string sigBitName(const RTLIL::SigBit &a_SigBit)
+    {
         if (a_SigBit.is_wire()) {
-            RTLIL::Wire* w = a_SigBit.wire;
+            RTLIL::Wire *w = a_SigBit.wire;
             return RTLIL::unescape_id(w->name);
         } else {
-            switch (a_SigBit.data)
-            {
-            case RTLIL::State::S0: return "1'b0";
-            case RTLIL::State::S1: return "1'b1";
-            case RTLIL::State::Sx: return "1'bx";
-            case RTLIL::State::Sz: return "1'bz";
-            case RTLIL::State::Sa: return "-";
-            case RTLIL::State::Sm: return "m";
+            switch (a_SigBit.data) {
+            case RTLIL::State::S0:
+                return "1'b0";
+            case RTLIL::State::S1:
+                return "1'b1";
+            case RTLIL::State::Sx:
+                return "1'bx";
+            case RTLIL::State::Sz:
+                return "1'bz";
+            case RTLIL::State::Sa:
+                return "-";
+            case RTLIL::State::Sm:
+                return "m";
             }
             return "?";
         }
@@ -903,10 +837,10 @@
 
     // ..........................................
 
-    void processPort (RTLIL::Cell* a_Cell, const DspPortType& a_PortRule) {
+    void processPort(RTLIL::Cell *a_Cell, const DspPortType &a_PortRule)
+    {
 
-        log_debug(" Attempting flip-flop integration for %s.%s of %s\n",
-            a_Cell->type.c_str(), a_PortRule.name.c_str(), a_Cell->name.c_str());
+        log_debug(" Attempting flip-flop integration for %s.%s of %s\n", a_Cell->type.c_str(), a_PortRule.name.c_str(), a_Cell->name.c_str());
 
         // Check if the port can be used for FF integration
         log_assert(a_Cell->output(a_PortRule.name) || a_Cell->input(a_PortRule.name));
@@ -922,19 +856,16 @@
         // Collect flip-flops, identify their group count
         dict<FlopData, int> groups;
 
-        std::vector<std::pair<RTLIL::Cell*, int>> flops
-            (sigbits.size(), std::make_pair(nullptr, -1));
+        std::vector<std::pair<RTLIL::Cell *, int>> flops(sigbits.size(), std::make_pair(nullptr, -1));
 
-        for (size_t i=0; i<sigbits.size(); ++i) {
+        for (size_t i = 0; i < sigbits.size(); ++i) {
             auto sigbit = sigbits[i];
             if (!sigbit.wire) {
                 continue;
             }
 
             // Skip bits out of the specified range
-            if ((a_PortRule.bits.first  >= 0 && (int)i < a_PortRule.bits.first) ||
-                (a_PortRule.bits.second >= 0 && (int)i > a_PortRule.bits.second))
-            {
+            if ((a_PortRule.bits.first >= 0 && (int)i < a_PortRule.bits.first) || (a_PortRule.bits.second >= 0 && (int)i > a_PortRule.bits.second)) {
                 continue;
             }
 
@@ -970,8 +901,8 @@
             }
 
             // Get the sink, check if this is a flip-flop
-            auto& other = *others.begin();
-            auto* flop  = other.cell;
+            auto &other = *others.begin();
+            auto *flop = other.cell;
 
             if (flop == nullptr) {
                 if (!other.port.empty()) {
@@ -988,12 +919,11 @@
             }
 
             // Check if the connection goes to the data input/output port
-            const auto& flopType = m_FlopTypes.at(flop->type);
+            const auto &flopType = m_FlopTypes.at(flop->type);
             RTLIL::IdString flopPort;
             if (a_Cell->output(a_PortRule.name)) {
                 flopPort = flopType.ports.at(RTLIL::escape_id("d"));
-            }
-            else if (a_Cell->input(a_PortRule.name)) {
+            } else if (a_Cell->input(a_PortRule.name)) {
                 flopPort = flopType.ports.at(RTLIL::escape_id("q"));
             }
 
@@ -1010,17 +940,15 @@
             // Get parameters to be mapped to the DSP according to the port
             // rule.
             dict<RTLIL::IdString, RTLIL::Const> mappedParams;
-            for (const auto& it : a_PortRule.params.map) {
+            for (const auto &it : a_PortRule.params.map) {
                 if (flop->hasParam(it.second)) {
-                    const auto& value = flop->getParam(it.second);
+                    const auto &value = flop->getParam(it.second);
                     mappedParams.insert(std::make_pair(it.first, value));
                 }
             }
 
             // Store the flop and its data
-            auto res = groups.insert(
-                std::make_pair(getFlopData(flop, mappedParams),groups.size())
-            );
+            auto res = groups.insert(std::make_pair(getFlopData(flop, mappedParams), groups.size()));
             flops[i] = std::make_pair(flop, res.first->second);
         }
 
@@ -1037,7 +965,7 @@
         }
 
         // Validate the flip flop data agains the DSP cell
-        const auto& flopData = groups.begin()->first;
+        const auto &flopData = groups.begin()->first;
         if (!checkFlopDataAgainstDspPort(flopData, a_Cell, a_PortRule)) {
             log_debug("  flip-flop vs. DSP check failed\n");
             return;
@@ -1045,27 +973,22 @@
 
         // Debug log
         log(" %s %s.%s\n", a_Cell->type.c_str(), a_Cell->name.c_str(), a_PortRule.name.c_str());
-        for (size_t i=0; i<flops.size(); ++i) {
+        for (size_t i = 0; i < flops.size(); ++i) {
             if (flops[i].first != nullptr) {
-                log_debug("  %2zu. (%d) %s %s\n", i,
-                    flops[i].second,
-                    flops[i].first->type.c_str(), flops[i].first->name.c_str());
-            }
-            else if ((a_PortRule.bits.first  >= 0 && (int)i < a_PortRule.bits.first) ||
-                     (a_PortRule.bits.second >= 0 && (int)i > a_PortRule.bits.second))
-            {
+                log_debug("  %2zu. (%d) %s %s\n", i, flops[i].second, flops[i].first->type.c_str(), flops[i].first->name.c_str());
+            } else if ((a_PortRule.bits.first >= 0 && (int)i < a_PortRule.bits.first) ||
+                       (a_PortRule.bits.second >= 0 && (int)i > a_PortRule.bits.second)) {
                 log_debug("  %2zu. (excluded)\n", i);
-            }
-            else {
+            } else {
                 log_debug("  %2zu. None\n", i);
             }
         }
 
         // Reconnect data signals, mark the flip-flop for removal
-        const auto& flopType = m_FlopTypes.at(flopData.type);
-        for (size_t i=0; i<flops.size(); ++i) {
+        const auto &flopType = m_FlopTypes.at(flopData.type);
+        for (size_t i = 0; i < flops.size(); ++i) {
 
-            auto* flop = flops[i].first;
+            auto *flop = flops[i].first;
             if (flop == nullptr) {
                 continue;
             }
@@ -1073,14 +996,12 @@
             RTLIL::IdString port;
             if (a_Cell->output(a_PortRule.name)) {
                 port = flopType.ports.at(RTLIL::escape_id("q"));
-            }
-            else if (a_Cell->input(a_PortRule.name)) {
+            } else if (a_Cell->input(a_PortRule.name)) {
                 port = flopType.ports.at(RTLIL::escape_id("d"));
             }
-            
+
             if (!flop->hasPort(port)) {
-                log_error("  cell '%s' does not have port '%s'!\n",
-                    flop->type.c_str(), port.c_str());
+                log_error("  cell '%s' does not have port '%s'!\n", flop->type.c_str(), port.c_str());
             }
 
             sigbits[i] = SigBit(RTLIL::Sx);
@@ -1096,33 +1017,31 @@
 
         // Reconnect (map) control signals. Connect the default value if
         // a particular signal is not present in the flip-flop.
-        for (const auto& it : a_PortRule.assoc) {
-            const auto& key  = it.first;
-            const auto& port = it.second.first;
- 
+        for (const auto &it : a_PortRule.assoc) {
+            const auto &key = it.first;
+            const auto &port = it.second.first;
+
             auto conn = RTLIL::SigBit(RTLIL::SigChunk(it.second.second));
             if (flopData.conns.count(key)) {
                 conn = flopData.conns.at(key);
             }
 
-            log_debug("  connecting %s.%s to %s\n", a_Cell->type.c_str(),
-                port.c_str(), sigBitName(conn).c_str());
+            log_debug("  connecting %s.%s to %s\n", a_Cell->type.c_str(), port.c_str(), sigBitName(conn).c_str());
             a_Cell->setPort(port, conn);
             m_DspChanges[a_Cell].conns.insert(port);
         }
 
         // Connect control signals according to DSP port rule
-        for (const auto& it : a_PortRule.connect) {
-            log_debug("  connecting %s.%s to %s\n", a_Cell->type.c_str(),
-                it.first.c_str(), it.second.as_string().c_str());
+        for (const auto &it : a_PortRule.connect) {
+            log_debug("  connecting %s.%s to %s\n", a_Cell->type.c_str(), it.first.c_str(), it.second.as_string().c_str());
             a_Cell->setPort(it.first, it.second);
             m_DspChanges[a_Cell].conns.insert(it.first);
         }
 
         // Map parameters (port rule)
-        for (const auto& it : a_PortRule.params.map) {            
+        for (const auto &it : a_PortRule.params.map) {
             if (flopData.params.dsp.count(it.second)) {
-                const auto& param = flopData.params.dsp.at(it.second);
+                const auto &param = flopData.params.dsp.at(it.second);
                 log_debug("  setting param '%s' to '%s'\n", it.first.c_str(), param.decode_string().c_str());
                 a_Cell->setParam(it.first, param);
                 m_DspChanges[a_Cell].params.insert(it.first);
@@ -1130,9 +1049,9 @@
         }
 
         // Map parameters (flip-flop rule)
-        for (const auto& it : flopType.params.map) {            
+        for (const auto &it : flopType.params.map) {
             if (flopData.params.dsp.count(it.second)) {
-                const auto& param = flopData.params.dsp.at(it.second);
+                const auto &param = flopData.params.dsp.at(it.second);
                 log_debug("  setting param '%s' to '%s'\n", it.first.c_str(), param.decode_string().c_str());
                 a_Cell->setParam(it.first, param);
                 m_DspChanges[a_Cell].params.insert(it.first);
@@ -1140,14 +1059,14 @@
         }
 
         // Set parameters (port rule)
-        for (const auto& it : a_PortRule.params.set) {
+        for (const auto &it : a_PortRule.params.set) {
             log_debug("  setting param '%s' to '%s'\n", it.first.c_str(), it.second.decode_string().c_str());
             a_Cell->setParam(it.first, it.second);
             m_DspChanges[a_Cell].params.insert(it.first);
         }
 
         // Set parameters (flip-flop rule)
-        for (const auto& it : flopType.params.set) {
+        for (const auto &it : flopType.params.set) {
             log_debug("  setting param '%s' to '%s'\n", it.first.c_str(), it.second.decode_string().c_str());
             a_Cell->setParam(it.first, it.second);
             m_DspChanges[a_Cell].params.insert(it.first);
@@ -1158,21 +1077,18 @@
 
     /// Collects flip-flop connectivity data and parameters which defines the
     /// group it belongs to.
-    FlopData getFlopData (RTLIL::Cell* a_Cell,
-                          const dict<RTLIL::IdString, RTLIL::Const>& a_ExtraParams)
+    FlopData getFlopData(RTLIL::Cell *a_Cell, const dict<RTLIL::IdString, RTLIL::Const> &a_ExtraParams)
     {
-        FlopData data (a_Cell->type);
+        FlopData data(a_Cell->type);
 
         log_assert(m_FlopTypes.count(a_Cell->type) != 0);
-        const auto& flopType = m_FlopTypes.at(a_Cell->type);
+        const auto &flopType = m_FlopTypes.at(a_Cell->type);
 
         // Gather connections to control ports
-        for (const auto& it : flopType.ports) {
+        for (const auto &it : flopType.ports) {
 
             // Skip "D" and "Q" as they connection will always differ.
-            if (it.first == RTLIL::escape_id("d") ||
-                it.first == RTLIL::escape_id("q"))
-            {
+            if (it.first == RTLIL::escape_id("d") || it.first == RTLIL::escape_id("q")) {
                 continue;
             }
 
@@ -1187,24 +1103,24 @@
         }
 
         // Gather flip-flop parameters that need to match
-        for (const auto& it : flopType.params.matching) {
+        for (const auto &it : flopType.params.matching) {
             log_assert(a_Cell->hasParam(it));
             data.params.flop.insert(std::make_pair(it, a_Cell->getParam(it)));
         }
 
         // Gather flip-flop parameters to be mapped to the DSP as well
-        for (const auto& it : flopType.params.map) {
+        for (const auto &it : flopType.params.map) {
             log_assert(a_Cell->hasParam(it.second));
             data.params.flop.insert(std::make_pair(it.second, a_Cell->getParam(it.second)));
         }
 
         // Gather DSP parameters and their values to be set to too
-        for (const auto& it : flopType.params.set) {
+        for (const auto &it : flopType.params.set) {
             data.params.dsp.insert(it);
         }
 
         // Append extra DSP parameters
-        for (const auto& it : a_ExtraParams) {
+        for (const auto &it : a_ExtraParams) {
             data.params.dsp.insert(it);
         }
 
@@ -1213,7 +1129,8 @@
 
     /// Retrieves a list of sinks driven by the given cell pin.
     /// TODO: This is slow, need to make a lookup for that.
-    pool<CellPin> getSinks (const CellPin& a_Driver) {
+    pool<CellPin> getSinks(const CellPin &a_Driver)
+    {
 
         auto module = a_Driver.cell->module;
         pool<CellPin> sinks;
@@ -1223,7 +1140,7 @@
 
         // Get the driver sigbit
         auto driverSigspec = a_Driver.cell->getPort(a_Driver.port);
-        auto driverSigbit  = m_SigMap(driverSigspec.bits().at(a_Driver.bit));
+        auto driverSigbit = m_SigMap(driverSigspec.bits().at(a_Driver.bit));
 
         // Look for connected sinks
         for (auto cell : module->cells()) {
@@ -1288,7 +1205,8 @@
 
     /// Finds a driver for the given cell pin
     /// TODO: This is slow, need to make a lookup for that.
-    CellPin getDriver (const CellPin& a_Sink) {
+    CellPin getDriver(const CellPin &a_Sink)
+    {
         auto module = a_Sink.cell->module;
 
         // The sink has to be an input pin
@@ -1296,7 +1214,7 @@
 
         // Get the sink sigbit
         auto sinkSigspec = a_Sink.cell->getPort(a_Sink.port);
-        auto sinkSigbit  = m_SigMap(sinkSigspec.bits().at(a_Sink.bit));
+        auto sinkSigbit = m_SigMap(sinkSigspec.bits().at(a_Sink.bit));
 
         // Look for connected top-level input ports
         for (auto conn : module->connections()) {
@@ -1363,4 +1281,3 @@
 } DspFF;
 
 PRIVATE_NAMESPACE_END
-