commit 0eaceddc5fc0a4d119302d292a5bf8c0b3c14dd3
author Kamil Rakoczy <krakoczy@antmicro.com> Wed Apr 05 14:07:13 2023 +0200
committer Kamil Rakoczy <krakoczy@antmicro.com> Tue Apr 11 10:40:03 2023 +0200
tree c5142269cff8dfa2556accb8e893c428a0911915
parent 60fc56f592333e588b5f3e5841f19112641e9ca1

systemverilog-plugin: apply custom simplification step to wiretype while resolving wiretype

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index a3f1315..54dfc50 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -412,6 +412,7 @@
     wiretype_ast = AST_INTERNAL::current_scope[wiretype_node->str];
     // we need to setup current top ast as this simplify
     // needs to have access to all already defined ids
+    simplify_sv(wiretype_ast, nullptr);
     while (simplify(wire_node, true, false, false, 1, -1, false, false)) {
     }
     log_assert(!wiretype_ast->children.empty());