)]}'
{
  "commit": "0eaceddc5fc0a4d119302d292a5bf8c0b3c14dd3",
  "tree": "c5142269cff8dfa2556accb8e893c428a0911915",
  "parents": [
    "60fc56f592333e588b5f3e5841f19112641e9ca1"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Apr 05 14:07:13 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Apr 11 10:40:03 2023 +0200"
  },
  "message": "systemverilog-plugin: apply custom simplification step to wiretype while resolving wiretype\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a3f131584e7b227c1be191144a60041a76018252",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "54dfc50055709300104c435d5b65ecfbed9a3c86",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}